Slide 1EE100 Summer 2008 Bharathwaj Muthuswamy

EE100Su08 Lecture #17 (August 4th 2008)• OUTLINE

– HW #3s-#6s: Pick up from lab, regrades: talk to Bart (HW #4s are in lab as well)

– QUESTIONS?– Lecture schedule:

• Today: wrap up transistors• Wednesday (08/06): Review• Friday (08/08), Monday (08/11): NO LECTURE• Wednesday (08/13): TA review• Friday (08/15): Final exam

– Transistor introduction (MOSFETs)– Simple transistor circuit: resistive inverter– Transistor logic circuits

• Reading– Reader: Chapter 4 and 5 (concentrate on logic applications).

Slide 2EE100 Summer 2008 Bharathwaj Muthuswamy

MOSFET• NMOS: Three regions of

operation– VDS and VGS normally

positive valus– VGS<Vt :cut off mode, IDS=0

for any VDS

– VGS>Vt :transistor is turned on

• VDS< VGS-Vt: Triode Region

• VDS> VGS-Vt: Saturation Region

• Boundary GS t DSv V v− =

2W KPKL

=

( )2)(22 DSDStGSD vvVvKP

LWi −−⋅=

( )22 tGSD VvKP

LWi −=

tto VVNote =:

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Inverter = NOT Gate

VoutVin

Vin

Vout

VV/2

Ideal Transfer Characteristics

Slide 10EE100 Summer 2008 Bharathwaj Muthuswamy

VDD/RD

VDD

NMOS Resistor Pull-Up

vDS

iD

0

vOUT

vIN0

VDD

RD

+

vDS = vOUT

–

iD

+vIN

–

VDD

RD

+

vDS = vOUT

–

iD

+vIN

–

Circuit: Voltage-Transfer Characteristic

VDD

VT

0110FA

AF

increasingvGS = vIN > VT

vGS = vin ≤ VT

vIN = VDD

VDD

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Slide 12EE100 Summer 2008 Bharathwaj Muthuswamy

Disadvantages of NMOS Logic Gates

• Large values of RD are required in order to– achieve a low value of VOL

– keep power consumption low

Large resistors are needed, but these take up a lot of space.

• One solution is to replace the resistor with an NMOSFET that is always on.

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The CMOS Inverter: Intuitive Perspective

VDD

Rn

VIN = VDD

CIRCUIT SWITCH MODELS

VDD

Rp

VIN = 0 V

VOUT VOUT

VOL = 0 V VOH = VDD

Low static power consumption, sinceone MOSFET is always off in steady state

VDD

VIN VOUT

S

D

G

G S

D

Slide 14EE100 Summer 2008 Bharathwaj Muthuswamy

Features of CMOS Digital Circuits

• The output is always connected to VDD or GNDin steady state→ Full logic swing; large noise margins→ Logic levels are not dependent upon the relative

sizes of the devices (“ratioless”)

• There is no direct path between VDD and GNDin steady state→ no static power dissipation

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NMOS NAND Gate

• Output is low only if both inputs are highVDD

RD

A

B

F

Truth Table

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NMOS NOR Gate

• Output is low if either input is high

VDD

RD

A B

F

011001010100FBA

Truth Table

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An NMOSFET is a closed switch when the input is high

N-Channel MOSFET Operation

NMOSFETs pass a “strong” 0 but a “weak” 1

Y = X if A and BY = X if A or B

BA

XB

A

XY Y

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A PMOSFET is a closed switch when the input is low

P-Channel MOSFET Operation

PMOSFETs pass a “strong” 1 but a “weak” 0

Y = X if A and B= (A + B) Y = X if A or B

= (AB)

BA

XB

A

XY Y

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Pull-Down and Pull-Up Devices• In CMOS logic gates, NMOSFETs are used to connect

the output to GND, whereas PMOSFETs are used to connect the output to VDD.– An NMOSFET functions as a pull-down device when it

is turned on (gate voltage = VDD)– A PMOSFET functions as a pull-up device when it is

turned on (gate voltage = GND)

F(A1, A2, …, AN)

PMOSFETs only

NMOSFETs only…

…

Pull-upnetwork

Pull-downnetwork

VDD

A1A2AN

A1A2AN

input signals

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CMOS NAND Gate

011101110100FBA

A

F

B

A B

VDD

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CMOS NOR Gate

A

F

B

A

B

VDD

011001010100FBA

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