ECE 4680 Computer Architecture

Verilog Presentation I.

Verilog HDL

Outline

• What is Verilog?• Basic HDL Concepts• Verilog Language Rules and Syntax• Behavioral and Structural Models• Control Statement• Test Methodology• Examples

HDL -Hardware Design LanguagesA Hardware Description Language is a language used to describe a digital system, for example, a computer or a component of a computer. One may describe a digital system at several levels.

Example:Switch level: wires, resistors and transistors Gate level: logical gates and flip flops Register Transfer Level (RTL): registers and the transfers of information between registers.

Today Two Major HDLs in Industry· VHDL· Verilog HDL

First Verilog Example – An AND Gate

module and (out, in1, in2); input in1, in2; output out;

assign out = in1 & in2;

endmodule

In1

in2out

VHDL Verses Verilog HDL

VHDL (“V” short for VHSIC)[Very High Speed Integrated Circuits]• Designed for and sponsored by US Department of Defense.• Designed by committee (1981- 1985).• Syntax based on Ada programming language.• VHDL was made an IEEE Standard in 1987

Verilog HDL• Verilog was introduced in 1985 by Gateway Design System Corporation, now a part of Cadence Design Systems, Inc.'s Systems Division.•Verilog was made an IEEE Standard in 1995 •Syntax based on C programming language.

Verilog HDL vs. VHDL

Design Methodology

HDLSpecification

Structure and Function(Behavior) of a Design

Simulation

Verification: DesignBehave as Required?

Functional: I/O BehaviorRegister-Level (Architectural)

Logic-Level (Gates)Transistor-Level (Electrical)Timing: Waveform Behavior

Synthesis

Generation: MapSpecification toImplementation

Verilog Identifiers An identifier (name) in Verilog is composed of a

space-free sequence of uppercase and lowercase letters from alphabet, the digits(0,1,….9), the underscore( _ ) and the $ symbol.

Verilog is a case sensitive language.e.g. c_out_bar or C_OUT_BAR

Verilog treats these as different names. The name of a variable may not begin with a digit or

$, and may up to 1,024 characters long.e.g. clock_, state_3

Verilog Statement Terminator Verilog models consist of a list of statements declaring

relationships between a model and its environment, and between signals within a model.E.g. module and endmodule

Statements are terminated by a semicolon( ; )

module full_addr (A, B, Cin, S, Cout); input A, B, Cin; output S, Cout; assign {Cout, S} = A + B + Cin;endmodule

Verilog comments There are two kinds of comments:

Single line and multiline A single-line comment begins with two forward slashes(//) A multiline comment begins with the pair of characters /*

and terminate with the characters */e.g. // This is a single-line comments/* This is a multiline comments

more comments here………………………………….

*/

Verilog Numbers Numbers are stores as binary words in the host machine. <size><base format><number> form where <size> is the size of the constant in the number of bits, <base format> is the single character ' followed by one of the following characters b, d, o and h. There are four base

specifiers: binary(b or B), decimal(d or D), hexadecimal (h or H), and octal(o or O).

<number> contains unsigned digits. Sized Numbers : can be sized to a specified word length

12’b0000_0100_0110 - binary number with 12 bits (_ is ignored) 12’h046 - hexadecimal number with 12 bits

Unsized NumbersIf a number is given without a size, it will be stored in a word having a length of at least 32 bits.e.g. ‘HAA is stored having a word length of 32 bits as0000_0000_0000_0000_0000_0000_1010_1010.

A number without a base will be interpreted as a decimal value

Verilog Operators I

Verilog Operators II

Verilog Value Logic System

Data type for signals Bits - value on a wire

0, 1 X - unknow value Z - a high impedance value, tri-state buffer

Vectors of bits A[3:0] - vector of 4 bits: A[3], A[2], A[1], A[0]

Concatenating bits/vectors into a vector B[7:0] = {A[3], A[3], A[3], A[3], A[3:0]}; B[7:0] = {3{A[3]}, A[3:0]};

Verilog Data Types- Constants Two kinds of data in Verilog:

Constant and Variables

Constant: is declared with the keyword parameter in a statement assigning a name and a value to the constant

The value of a constant is fixed during simulation.

e.g. parameter HIGH_INDEX= 31; // integer parameter BYTE_SIZE=8;

Verilog Data Types -Variables Two basic families of data types for variables

Nets and Registers Net variables – e.g. wire

Variable used simply to connect components together Usually corresponds to a wire in the circuit, like wires in a

physical circuit and establish connectivity between modules Register variables – e.g. Reg

Variable used to store data as part of a behavioral description Like variables in ordinary procedural languages

Notes: Reg should only be used with always blocks (sequential

logic, to be presented …) The reg variables store the last value that was procedurally

assigned to them whereas the wire variables represent physical connections between structural entities such as gates.

Verilog Continuous Assignment A continuous assignment statement is declared with the

keyword assign, followed by a net(e.g. type wire) variable, an assignment operator(=), and an expression.

assign corresponds to a connection or a simple component with the described function

Target is NEVER a reg variable

assign A = X | (Y & ~Z);

assign B[3:0] = 4'b01XX;

assign C[15:0] = 16'h00ff;

assign #3 {Cout, S[3:0]} = A[3:0] + B[3:0] + Cin;

use of arithmetic operatormultiple assignment (concatenation)

delay of performing computation, only used by simulator, not synthesis

use of Boolean operators(~ for bit-wise, ! for logical negation)

bits can take on four values(0, 1, X, Z)

variables can be n-bits wide(MSB:LSB)

Procedural Assignment & String

• Procedural assignments have the form <reg variable> = <expression>

where the <reg variable> must be a register or memory.e.g. reg enable, d;

#1 enable = 0;16  #1 d = 0;

• String is a sequence of characters enclosed in “” quotes,e.g., “digital”, “I am a student of ECE4680 class”

Any digital system is a set of modules.The modules may run concurrently, but usually there is one top level module to specify a closed system containing both test data and hardware models.The top level module invokes instances of other modules. A module is never called, is instantiated. Modules can be specified behaviorally or structurally (or a combination of the two). A behavioral specification defines the behavior of a digital system using traditional programming language constructs, e. g., if else, assignment statements. A structural specification expresses the behavior of a digital system (module) as a hierarchical interconnection ofsub modules.

Program Structure: Modules

Simple Behavioral Model Combinational logic

Describe output as a function of inputs Note use of assign keyword: continuous

assignment

module and_gate (out, in1, in2); input in1, in2; output out;

assign out = in1 & in2;

endmodule

The structure of a module is the following: module <module name> (<port list>); <declares> <module items> endmodule

Where<module name> is an identifier that uniquely names the module. <port list> is a list of input, output and inout ports which are used to connect to other modules. <declares> specifies data objects as registers, memories & wires as wells as procedural constructs such as functions & tasks. <module items> may be initial constructs, always constructs, continuous assignments or instances of modules.

The structure of a module

Verilog Module Example 1-bit Adder

Corresponds to a circuit component “Parameter list” is the list of external connections, “ports” Ports are declared “input”, “output” or “inout”

inout ports used on tri-state buses Port declarations imply that the variables are wires

module full_addr (A, B, Cin, S, Cout); input A, B, Cin; output S, Cout; assign {Cout, S} = A + B + Cin;endmodule

module name

declares

ports

module item

Mixed Structural/Behavioral Model

Example 4-bit ripple addermodule full_addr (S, Cout, A, B, Cin ); input A, B, Cin; output S, Cout;

assign {Cout, S} = A + B + Cin; Behaviorendmodule

module adder4 (S, Cout, A, B, Cin); input [3:0] A, B; input Cin; output [3:0] S; output Cout; wire C1, C2, C3;

full_addr fa0 (S[0], C1, A[0], B[0], Cin); Structural full_addr fa1 (S[1], C2, A[1], B[1], C1); full_addr fa2 (S[2], C3, A[2], B[2], C2); full_addr fa3 (S[3], Cout, A[3], B[3], C3);endmodule

// Behavioral Model of a NAND gate module NAND(inp1, inp2, out); input inp1, inp2;

output out; // inp1, inp2 and out are labels on wires. // continuous assign statement

assign out = ~(inp1 & inp2); endmodule

Behavioral Model of a NAND gate

Structural Model of a AND gate

/*Structural specification of a module AND using NAND gates*/

module AND(in1, in2, out); input in1, in2; output out; wire w1; NAND NAND1(in1, in2, w1); // instantiation of theNAND NAND2(w1, w1, out); // module NAND

Endmodule

1-bit Comparator Example module Comparator1 (A, B, Equal, Alarger, Blarger);

input A, B; output Equal, Alarger, Blarger;

assign Equal = (A & B) | (~A & ~B); assign Alarger = (A & ~B); assign Blarger = (~A & B);endmodule

A

B

L2

L3

L1Equal

Alarger

Blarger

4-bit Comparator Example// Make a 4-bit comparator from 4 1-bit comparators

module Compare4(A4, B4, Equal, Alarger, Blarger); input [3:0] A4, B4; output Equal, Alarger, Blarger; wire e0, e1, e2, e3, Al0, Al1, Al2, Al3, B10, Bl1, Bl2, Bl3; Compare1 cp0(A4[0], B4[0], e0, Al0, Bl0); Compare1 cp1(A4[1], B4[1], e1, Al1, Bl1); Compare1 cp2(A4[2], B4[2], e2, Al2, Bl2); Compare1 cp3(A4[3], B4[3], e3, Al3, Bl3); assign Equal = (e0 & e1 & e2 & e3); assign Alarger = (Al3 | (Al2 & e3) |

(Al1 & e3 & e2) | (Al0 & e3 & e2 & e1));

assign Blarger = (~Alarger & ~Equal);endmodule

Procedural Blocks There are two types of procedural blocks in Verilog

initial - single-pass behavior : initial blocks execute only once at time zero (start execution at time zero). always - cyclic behavior : always blocks loop to execute over and over again, in other words as name means, it executes always.

Procedural assignment may only appear in initial and always constructs.

The initial and always constructs are used to model sequential logic. Continuous statement is used to model combinational

logic.

Example - initial

module initial_example();2 reg clk,reset,enable,data;34

initial begin5 clk = 0;6 reset = 0;7 enable = 0;8 data = 0;9

end1011\endmodule  In the above example, the initial block execution at time 0. Initial block without waiting just executed all the statements

within begin and end statement.

Example - always module always_example();2

reg clk,reset,enable,q_in,data;34always @ (posedge clk)5begin

if (reset) begin6 data <= 0;7

end else if (enable) begin 8 

data <= q_in;9end

end11endmodule 

In always block, when the trigger event occurs, the code inside begin and end is executed and the once again the always block waits for next posedge of clock. This process of waiting and executing on event is repeated till simulation stops.

• Control Constructs Can be used in the procedural sections of code. • Selection - if and case Statements

if (A == 4) begin

B = 2; end else begin

B = 4; end

case (<expression>) <value1>: <statement>

<value2>: <statement> default: <statement>

endcase

Control Constructs

Verilog Control Statement – if I.• Same as C if statement// Simple 4-1 muxmodule mux4 (sel, A, B, C, D, Y);

input [1:0] sel; // 2-bit control signalinput A, B, C, D;output Y;reg Y; // target of assignment

always @(sel or A or B or C or D) if (sel == 2’b00) Y = A; else if (sel == 2’b01) Y = B; else if (sel == 2’b10) Y = C; else if (sel == 2’b11) Y = D;

endmodule

Verilog Control Statement – if II.// Simple 4-1 muxmodule mux4 (sel, A, B, C, D, Y);

input [1:0] sel; // 2-bit control signalinput A, B, C, D;output Y;reg Y; // target of assignment

always @(sel or A or B or C or D) if (sel[0] == 0) if (sel[1] == 0) Y = A; else Y = B; else if (sel[1] == 0) Y = C; else Y = D;endmodule

Verilog case-Simple 4-1 mux Sequential execution of cases

Only first case that matches is executed Default case can be used

// Simple 4-1 muxmodule mux4 (sel, A, B, C, D, Y);

input [1:0] sel; // 2-bit control signalinput A, B, C, D;output Y;reg Y; // target of assignment

always @(sel or A or B or C or D) case (sel) 2’b00: Y = A; 2’b01: Y = B; 2’b10: Y = C; 2’b11: Y = D; endcaseendmodule

Conditions tested intop to bottom order

Verilog case-Simple Binary Encoder

Without the default case, this example would create a latch for Y Assigning X to a variable means synthesis is free to assign any value

module encode (A, Y);

input [7:0] A; // 8-bit input vector

output [2:0] Y; // 3-bit encoded output

reg [2:0] Y; // target of assignment

always @(A)

case (A)

8’b00000001: Y = 0;

8’b00000010: Y = 1;

8’b00000100: Y = 2;

8’b00001000: Y = 3;

8’b00010000: Y = 4;

8’b00100000: Y = 5;

8’b01000000: Y = 6;

8’b10000000: Y = 7;

default: Y = 3’bX; // Don’t care when input is not 1-hot

endcase

endmodule

Verilog case – Decodermodule decoder_using_case (8binary_in , decoder_out , enable);12input [3:0] binary_in ;13 // 4 bit binary inputinput enable ;14 // Enable for the decoder11output [15:0] decoder_out ; // 16-bit out1516reg [15:0] decoder_out ;1718always @ (enable or binary_in)19begin20 decoder_out = 0;21 if (enable) begin22  case (binary_in)23 

4'h0 : decoder_out = 16'h0001;24 4'h1 : decoder_out = 16'h0002;25 4'h2 : decoder_out = 16'h0004;26  4'h3 : decoder_out = 16'h0008;27 4'h4 : decoder_out = 16'h0010;28 4'h5 : decoder_out = 16'h0020;29 4'h6 : decoder_out = 16'h0040;30 4'h7 : decoder_out = 16'h0080;31 4'h8 : decoder_out = 16'h0100;32 4'h9 : decoder_out = 16'h0200;33 4'hA : decoder_out = 16'h0400;34 4'hB : decoder_out = 16'h0800;35 4'hC : decoder_out = 16'h1000;36  4'hD : decoder_out = 16'h2000;37  4'hE : decoder_out = 16'h4000;38  4'hF : decoder_out = 16'h8000;39  

endcase40  End41End4243endmodule

for(i = 0; i < 10; i = i + 1) // for loopbegin $display("I = %0d", i);end

i = 0; //while statement acts in the normal fashion. while(i < 10) begin $display("I = %0d", i); i = i + 1; end

repeat (5) //repeats the block 5 times,begin

$display("I = %0d", i); i = i + 1; end

Repetition - for, while and repeat Statements

•A circuit must be tested and verified systematically to ensure that all of its logic has been exercised and found to be functionally correct.•A testbench is a separate Verilog module, which contains a stimulus generator, a response monitor and an instantiation of the unit under test.

•During simulation, the response monitor selectively gathers data on signals and displays them in a text or graphical format.

Test Methodology

Unit Under TestStimulus Generator Response Monitor

module test_AND (); //module to test the two other modules reg a, b; wire out1, out2; initial begin

a = 0; b = 0; // Test data #1 a = 1; #1 b = 1; #1 a = 0;

end initial begin // Set up monitoring $monitor("Time=%0d a=%b b=%b out1=%b out2=%b", $time, a, b, out1, out2); end

// Instances of modules AND and NAND NAND gate2(a, b, out1);

AND gate1(a, b, out2); endmodule

Testbench Example

// output for program above Time=0 a=0 b=0 out1=1 out2=0 Time=1 a=1 b=0 out1=1 out2=0Time=2 a=1 b=1 out1=0 out2=1 Time=3 a=0 b=1 out1=1 out2=0

Testbench Result

Note: $display is used for printing text or variables to stdout (screen), Syntax is same as printf. $monitor is bit different, $monitor keeps track of changes to the variablesthat are in the list ($time, a, b, out1, out2). When ever anyone of them changes, it prints their value, in the respective radix specified.

• The blocking assignment statement (= operator) acts much like in traditional programming languages. Blocking statement must complete execute before the next statement in the behavior can execute.

•The non-blocking (<= operator) evaluates all the right-hand sides for the current time unit and assigns the left-hand sides at the end of the time unit. Non-blocking assignment statements execute concurrently rather than sequentially.

Blocking and Non-blocking Procedural Assignments

reg [0:7] A, B; initial begin: init1

A = 3; #1 A = A + 1; // blocking procedural assignment B = A + 1; $display("Blocking: A= %b B= %b", A, B );

A = 3; #1 A <= A + 1; // non-blocking procedural assignment B <= A + 1; #1 $display("Non-blocking: A= %b B= %b", A, B );

end endmodule

Output is : Blocking: A= 00000100 B= 00000101 Non-blocking: A= 00000100 B= 00000100

Testing blocking & non-blocking assignment module blocking

Structural Model - XOR

module xor_gate ( out, a, b ); input a, b; output out; wire abar, bbar, t1, t2;

inverter invA (abar, a); inverter invB (bbar, b); and_gate and1 (t1, a, bbar); and_gate and2 (t2, b, abar); or_gate or1 (out, t1, t2);

endmodule

By default, identifiers are wires

invA

invB

A

B

outand1

and2

or1

t1

t2

2-to-1 MUX Behavioral Description

//Does not assume that we have // defined a 4-input mux.

//4-input mux behavioral descriptionmodule mux4 (in0, in1, in2, in3, select, out); input in0,in1,in2,in3; input [1:0] select; output out; reg out;

always @ (in0 in1 in2 in3 select)case (select)2’b00: out=in0;2’b01: out=in1;2’b10: out=in2;2’b11: out=in3;endcase

endmodule // mux4

Structural Model: 2-to1 MUX//2-input multiplexor in gatesmodule mux2 (in0, in1, select, out); input in0,in1,select; output out; wire s0,w0,w1;

not (s0, select); and (w0, s0, in0), (w1, select, in1); or (out, w0, w1);

endmodule // mux2

D Flip-Flop // D flip-flop Codemodule d_ff ( d, clk, q, q_bar);

input d ,clk;output q, q_bar;wire d ,clk;reg q, q_bar;always @ (posedge clk)

beginq <= d;1 q_bar <= !d;

Endendmodule

q

q_bar

d

clk

DFF

8-Bit Simple Up Counter Using D Flip-Flop

module up_counter ( out, enable, clk, reset);output [7:0] out;input enable, clk, reset;reg [7:0] out; //------------Internal Variables--------

//-------------Code Starts Here-------

always @(posedge clk)if (reset) beginout <= 8'b0 ;endelse if (enable) beginout <= out + 1;end

endmodule

Final thoughts Verilog looks like C, but it describes hardware

Multiple physical elements, Parallel activities Temporal relationships Basis for simulation and synthesis figure out the circuit you want, then figure out

how to express it in Verilog Understand the elements of the language

Modules, ports, wires, reg, primitive, continuous assignment, blocking statements, sensitivity lists, hierarchy

Best done through experience

1. Cadence Design Systems, Inc., Verilog-XL Reference Manual. 2. Ciletti, Michael D., Starting Guides to Verilog 2001, Prentice Hall 20043. World Wide Web Pages: http://www.eg.bucknell.edu/~cs320/Fall2003/verilog.htmlhttp://www.verilog.net/index.htmlhttp://www.eecs.berkeley.edu/~cullerhttp://www-inst.eecs.berkeley.edu/~cs150

References