Post on 10-Mar-2018
2/10/2012
1
Chapter 2
FET Biasing
Spring 2012
4th Semester Mechatronics
SZABIST, Karachi
CH 210 12
FET
Biasing
Course Support
humera.rafique@szabist.edu.pk
Office: 100 Campus (404)
Official: ZABdesk
https://sites.google.com/site/zabistmechatronics/home/spring-2012/ecd
ebooks: https://sites.google.com/site/zabistmechatronics/home/ebooks
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2
CH 2
FET
Biasing
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Chapter Contents
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• Fixed biased
• Self biased
• Voltage Divider Biasing
• Common Gate
• Configurations of D-MOSFETs
• Configurations of E-MOSFETs
• p-channel FET configurations
• Practical Applications
• Computer Analysis
3
CH 2
FET
Biasing
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4
CH 2
FET
Biasing
Introduction
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Common JFET Biasing Circuits:
JFET Biasing Circuits
• Fixed – Bias
• Self-Bias
• Voltage-Divider Bias
D-Type MOSFET Biasing Circuits
• Self-Bias
• Voltage-Divider Bias
E-Type MOSFET Biasing Circuits
• Feedback Configuration
• Voltage-Divider Bias
Introduction 5
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Basic Current Relationshipss
For all FETs:
For JFETS and D-Type MOSFETs:
For E-Type MOSFETs:
Introduction 6
CH 2
FET
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0 & G D SI A I I≅ =
2
P
GSDSSD
V
V1II
−−−−====
2TGSD )VV(kI −−−−====
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7
JFET Configurations
CH 2
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8
Fixed
Biased
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JFET Fixed Bias:
Fixed Biased 9
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JFET Fixed Bias:
Fixed Biased 10
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Plotting Shockley’s equation Finding the solution for the fixed-bias
configuration
Fixed Biased 11
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Measuring the quiescent values of ID and VGS
Fixed Biased 12
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JFET Fixed Bias:
Fixed Biased 13
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Biasing
0
D S D D D D
S
S D S
D S G S
G S G G
V V I R
V V
V V
V V
V V
= −
=
=
=
= −
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Example 7-1:
Determine the following:
Fixed Biased 14
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Example 7-1:
Fixed Biased 15
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Example 7-1:
Fixed Biased 16
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Computer Analysis
-8 -7 -6 -5 -4 -3 -2 -1 00
0.001
0.002
0.003
0.004
0.005
0.006
0.007
0.008
0.009
0.01
X: -2
Y: 0.005625
example 7-1
VGS (V)
ID (
mA
)
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Example 7-1:
Fixed Biased 17
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Computer Analysis
% JFET DC Biasing Configurations
% Fixed bias
% Example 7-1 Boylestad
RD = 2000; VGG= 2; VDD = 16; IDSS = 10/1000; Vp = -8;
VGS = Vp:0.1:0;
ID = IDSS*(1-VGS/Vp).^2;
plot(VGS,ID), grid on,
title('example 7-1') , xlabel('VGS (V)'), ylabel('ID (mA)')
% Fixed bias line
hold,
plot(-VGG,ID,'*')
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Self Bias
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JFET: Self Biased
Self Bias 19
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DC Analysis:
Self Bias 20
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( )
GS D S
DS DD D S D
S D S
D DS S DD RD
V I R
V V I R R
V I R
V V V V V
= −
= − +
=
= + = −
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Calculations:For the indicated loop,
To solve this equation:
• Select an ID < IDSS and use the component value of RS to calculate VGS
• Plot the point identified by ID and VGS. Draw a line from the origin of the
axis to this point.
• Plot the transfer curve using IDSS and
VP (VP = VGSoff in specification sheets) and a few points such as ID = IDSS / 4
and ID = IDSS / 2 etc.
The Q-point is located where the first line intersects the transfer curve. Use the value
of ID at the Q-point (IDQ) to solve for the other voltages:
Self Bias 21
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FET
Biasing
RDDDSDSD
SDS
DSDDDDS
VVVVV
RIV
)RR(IVV
−−−−====++++====
====
++++−−−−====
SDGS RIV −−−−====
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Calculations:
Self Bias 22
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Calculations:
Self Bias 23
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Example 7-2:Determine the following:
Self Bias 24
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Example 7-2:
Self Bias 25
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Example 7-2:
Self Bias 26
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Example 7-2:
Self Bias 27
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Example 7-2:
Self Bias 28
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Computer Analysis
-8 -7 -6 -5 -4 -3 -2 -1 00
1
2
3
4
5
6
7
8x 10
-3
X: -2.601
Y: 0.002601
Example 7-2
VGS (V)
ID (
mA
)
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Example 7-2:
Self Bias 29
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Biasing
Computer Analysis
%% EXAMPLE 7-2
% Self Bias Configuration
RD = 3300; Rs=1000; IDSS = 8/1000; Vp = -6; VDD = 20;
VGS = Vp:0.001:0;
ID = IDSS*(1-VGS/Vp).^2;
plot(VGS,ID), grid on,
title('Example 7-2') , xlabel('VGS (V)'), ylabel('ID (mA)')
% self bias line calculations
Vgs = -ID*Rs;
hold,
plot(Vgs, ID,'r.-')
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Example 7-3:Find the quiescent point for the given network: (Example 7.2)
Self Bias 30
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Example 7-3:Find the quiescent point for the given network: (Example 7.2)
Self Bias 31
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%% EXAMPLE 7-3
% Self Bias Configuration
RD = 3300; IDSS = 8/1000; Vp = -6; VDD = 20;
VGS = Vp:0.001:0;
ID = IDSS*(1-VGS/Vp).^2;
plot(VGS,ID), grid on,
title('Example 7-3') , xlabel('VGS (V)'), ylabel('ID (mA)')
% self bias line calculations for Rs = 100 Ohms
Rs=100;
Vgs = -ID*Rs;
hold,
plot(Vgs, ID,'r.-')
% self bias line calculations for Rs = 10k Ohms
Rs = 10000;
Vgs = -ID*Rs;
plot(Vgs, ID,'m.-')
Computer Analysis
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Example 7-3:Find the quiescent point for the given network: (Example 7.2)
Self Bias 32
CH 2
FET
Biasing
-8 -6 -4 -2 0 20
1
2
3
4
5
6
7
x 10-3
X: -0.6401
Y: 0.006401
Example 7-3
VGS (V)
ID (
mA
)
Computer Analysis
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Voltage
Divider Biased
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VDB:
Voltage Divider Bias 34
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IG = 0 A
ID responds to changes in VGS
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VDB:
Voltage Divider Bias 35
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The Q point is established by plotting a
line that intersects the transfer curve.
21
DD2G
RR
VRV
++++====
VG is equal to the voltage across divider
resistor R2:
Using Kirchhoff’s Law:
SDGGS RIVV −−−−====
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VDB:
Voltage Divider Bias 36
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FET
Biasing
• IG = 0 A and ID responds to changes in VGS
• Using the value of ID at the Q-point, solve for
the other variables in the voltage-divider bias
circuit:
2 DDG
1 2
DDR1 R2
1 2
DS DD D D S
D DD D D
S D S
R VV ;
R R
VI I
R R
V V I (R R )
V V I R
V I R
=+
= =+
= − +
= −
=
GS G D S
V V I R= −
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VDB Q-point:
Voltage Divider Bias 37
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Step 1
Plot the line by plotting two points:
• VGS = VG, ID = 0 A
• VGS = 0 V, ID = VG / RS
Step 2
Plot the transfer curve by plotting
IDSS, VP and the calculated values of
ID
Step 3
The Q-point is located where the line
intersects the transfer curve
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Effect of increasing RS:
Voltage Divider Bias 38
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Example 7-5:For the given network, find:
a. IDQ and VGSQ
b. VD and VS
c. VDS and VDG
Voltage Divider Bias 39
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Example 7-5:
Voltage Divider Bias 40
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Example 7-5:
Voltage Divider Bias 41
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%% EXAMPLE 7-5
% Voltage Divider Bias Configuration
R1 = 2.1*10^6; R2 = 270*10^3; RD = 2400;
IDSS = 8/1000; Vp = -4; VDD = 16;
VGS = Vp:0.1:0;
ID = IDSS*(1-VGS/Vp).^2;
plot(VGS,ID), grid on,
title('Example 7-5') , xlabel('VGS (V)')
ylabel('ID (A)')
% Load line (Voltage Divider Bias)
calculations
% Rs = 1.5k Ohms
Rs=1500;
Vg = VDD*R2/(R1+R2);
Vgs = Vg-(ID*Rs);
hold,
plot(Vgs, ID,'r.-')-12 -10 -8 -6 -4 -2 0 20
1
2
3
4
5
6
7
8x 10
-3
X: -7.594e-005
Y: 0.001215
Example 7-5
VGS (V)
ID (
A)
X: -1.801
Y: 0.002416
X: 1.823
Y: 0
X: -8
Y: 0.006549
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42
Common Gate
Configuration
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Common Gate:
Common Gate Configuration 43
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Common Gate:
Common Gate Configuration 44
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FET
Biasing
GS SS D S
V V I R= −
DS DD D D S
D DD D D
S D S
V V I (R R )
V V I R
V +I R
SS
SS
V
V
= + − +
= −
= −
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Example 7-4:
Determine the following: IDQ, VGSQ, VDS, VD and VS:
Common Gate Configuration 45
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Example 7-6:Determine the following: (RD = 1.5 kΩ, RS = 680 Ω, VDD = 12 V)
Common Gate Configuration 46
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Example 7-6:
Common Gate Configuration 47
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-9 -8 -7 -6 -5 -4 -3 -2 -1 00
0.002
0.004
0.006
0.008
0.01
0.012Example 7-6
VGS (V)
ID (
A)
X: 0
Y: 0
X: -5.007
Y: 0.007363
X: -2.62
Y: 0.003853
%% EXAMPLE 7-6: % Common Gate
Configuration
RD = 1500; IDSS = 12/1000; Vp = -6;
VDD = 12;
VGS = Vp:0.1:0;
ID = IDSS*(1-VGS/Vp).^2;
plot(VGS,ID), grid on,
title('Example 7-6') , xlabel('VGS (V)')
ylabel('ID (A)')
% Load line (Common Gate) calculations for
% Rs = 680 Ohms
Rs=680;
Vss = 0;
Vgs = Vss-(ID*Rs);
hold,
plot(Vgs, ID,'r.-')
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Special Case: VGSQ = 0 V:
Common Gate Configuration 48
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FET
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Q SSD D
I I=
DS DD D D
D
V V I R
V
0
DS
S
V
V V
= −
=
=
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49
D-MOSFETs
CH 2
FET
Biasing
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Configurations:
1. Voltage Divider
2. Self Bias
3. Common Gate Special Case
D-MOSFETs 50
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Voltage Divider Bias:
Example 7-7:
Determine the following:
a. Q-point
b. VDS
D-MOSFETs 51
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Example 7-8:
Determine the following: (Data of Ex. 7-7, RS = 150Ω )
D-MOSFETs 52
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Self Bias:
Example 7-9:
Determine the following, if RD = 6.2 k, RS = 2.4 k, IDSS = 8mA and VP = − 8V.
D-MOSFETs 53
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Common Gate (Special case):
Example 7-10:
Determine VDS for the following network:
D-MOSFETs 54
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55
E-MOSFETs
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Configurations:
1. Feedback Biasing Arrangement
2. Voltage Divider Biasing Arrangement
E-MOSFETs 56
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The transfer characteristic for the e-type MOSFET is very different from that
of a simple JFET or the d-type MOSFET.
E-MOSFETs 57
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Feedback Biasing Arrangement:
E-MOSFETs 58
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Biasing
IG = 0 A
VRG = 0 V
VDS = VGS
VGS = VDD – IDRD
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Feedback Biasing Q-point:
Step 1Plot the line using
• VGS = VDD, ID = 0 A• ID = VDD / RD , VGS = 0 V
Step 2Using values from the specification sheet, plot the transfer curve with
• VGSTh , ID = 0 A • VGS(on), ID(on)
Step 3The Q-point is located where the line and the transfer curve intersect
Step 4Using the value of ID at the Q-point, solve for the other variables in the bias circuit
E-MOSFETs 59
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Example 7-11:
Determine IDQ and VDSQ:
E-MOSFETs 60
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Example 7-11:
E-MOSFETs 61
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Voltage Divider Bias:Plotting the line and the transfer curve to find the Q-point:
E-MOSFETs 62
CH 2
FET
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21
DD2G
RR
VRV
++++====
)RR(IVV
RIVV
DSDDDDS
SDGGS
++++−−−−====
−−−−====
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Voltage Divider Bias Q-point:Step 1
Plot the line using • VGS = VG = (R2VDD) / (R1 + R2), ID = 0 A • ID = VG/RS , VGS = 0 V
Step 2Using values from the specification sheet, plot the transfer curve with
• VGSTh, ID = 0 A• VGS(on) , ID(on)
Step 3The point where the line and the transfer curve intersect is the Q-point.
Step 4Using the value of ID at the Q-point, solve for the other circuit values.
E-MOSFETs 63
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Example 7-12:Determine IDQ, VGSQ and VDS:
E-MOSFETs 64
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Example 7-12:Determine IDQ, VGSQ and VDS:
E-MOSFETs 65
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Summary 66
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Summary 67
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68
Design
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Example 7-15:Determine RS and RD:
Design 69
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Example 7-16:Determine RS when RD = 1800 Ω, R1 = 91kΩ, R2 = 47 kΩ, VDD = 16 V, VGSQ = -2V.
Design 70
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Example 7-17:Determine VDD and RD , when VDS = ½ VDD and ID = ID(on).
Design 71
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72
p-channel
FETs
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For p-channel FETs the same calculations and graphs are used, except that
the voltage polarities and current directions are reversed.
The graphs are mirror images of the n-channel graphs.
p-channel FETs 73
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p-channel JFET
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p-channel FETs 74
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p-channel D MOSFET (VDB)
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p-channel FETs 75
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p-channel E MOSFET (FB)
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p-channel FETs 76
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p-channel DMOSFET (VDB)
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p-channel FETs 77
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Example 7-18:Determine IDQ, VGSQ and VDS:
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78
Applications
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Applications:
1. Voltage Controlled Resistor
2. JFET Voltmeter
3. Timer Network
4. Fiber Optic System
5. MOSFET Relay Driver
Applications 79
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CH 110 12
Home Task 80FET
1. Exercise Problem 1, 2 and 4
2. Exercise Problem 7 and 11
3. Exercise Problem 13
4. Exercise Problem 15 and 17
5. Exercise Problem 19
6. Exercise Problem 21
7. Exercise Problem 25
8. Exercise Problem 31
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CH 110 12
Refernces 81FET
1. Bolestad
2. Paynter
3. Floyd
CH 2
FET
Biasing