Post on 16-Mar-2018
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T tb k Ch t 3
Digital Logic: Boolean Algebra and Gates
Textbook Chapter 3
Basic Logic Gates
CMPE12 – Summer 2009 02-2
XOR
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Truth Table The most basic
representation of a logic function
Lists the output for all possible input combinations
How many rows of the truth table needed? 2#inputs
X Y …A B …
OutputsInputs
X Y …A B …
OutputsInputs
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Truth Table Example
Inputs Output
A B Y
2#inputs
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Truth Table: Inverter Inverted signals are
denoted with an overbar
Or with a prime symbol
Input Output
A Y = A’
A’
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Truth Table: AND Gate The result of an AND
operation is 1 if and only if all inputs are 1
Inputs Output
A B Y = A · B
Depict AND by the multiplication symbol
A·B
Or by lumping the signals together
AB
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AB
We don’t really build these gates…
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Truth Table: OR Gate The result of an OR
operation is 1 if and only if any inputs are 1
Inputs Output
A B Y = A + B
Depict OR by the addition symbol
A+B
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About the Little Circle… The little circle is what inverts
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Sum of Products How do you get from a truth table to a logic
expression?
Sum of products is standard way of Sum of products is standard way of synthesizing simple circuits
Procedure:1. Find the rows with the ‘1’ output2. Write the product-form expression for the inputs
in that row (0=inverted, 1=normal)
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( , )3. Combine the products in step 2 into a sum (OR
the results of step 2)
Sum of Products1. Find the rows with the ‘1’
output2. Write the product-form
fA B Y
expression for the inputs in that row (0=inverted, 1=normal)
3. Combine the products in step 2 into a sum (OR the results of step 2)
0 0 0
0 1 1
1 0 1
1 1 0
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De Morgan’s Laws “Break the line, change the sign”
Two laws:A’ + B’ = (AB)’ A’ + B’ = (AB)’
A’ B’ = (A+B)’
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De Morgan’s Laws
(A + B)’ = A’B’ conversely (AB)’ = A’ + B’
“Break the line change the sign”Break the line, change the sign
A B A+B A A+B A B A·B
0 0
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0 1
1 0
1 1
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De Morgan’s Laws
(A + B)’ = A’B’ conversely (AB)’ = A’ + B’
“Break the line change the sign”Break the line, change the sign
A B AB A AB A B A+B
0 0
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0 1
1 0
1 1
De Morgan’s Laws In other words…
Push the bubbles through!
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De Morgan’s Laws and SOP Generate equivalent circuits
NAND/NAND
NOR/NOR NOR/NOR
We prefer NAND/NAND circuits Same transistor count as NOR
NANDs are faster
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Logical CompletenessA B C D
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
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1 0 1 1
1 1 0 0
1 1 1 0
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More Than Two Inputs? AND and OR gates can take any number of inputs
AND gives 1 if all inputs are 1
OR gives 1 if any input is 1 OR gives 1 if any input is 1
NAND?? NOR??
Not associative!
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Two-Way Multiplexer2-way multiplexer: the output is equal to one of the two inputs, based on a
S A B Y
0 0 0 0
selector 0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
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1 0 1 1
1 1 0 0
1 1 1 1
Two-Way Multiplexer
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Four-Way Multiplexer n-bit selector and 2n inputs, one output
output equals one of the inputs, depending on selectorselector
“Four-to-one mux”
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Two-to-Four Decoder n inputs, 2n outputs
exactly one output is 1 for each possible input pattern
Generates a walking-ones pattern
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Binary Addition and Half-Adder 0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
A half-adder is…
1 0 1
1 + 1 = ...
Bigger addition example:
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One-Bit Full Adder
A B Cin Cout S
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
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1 0 1
1 1 0
1 1 1
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Four-Bit Full Adder
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Masking Want to look only at certain bits of a binary word
Use a mask to remove the uninteresting bits
E l Example:
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Axioms of Boolean Algebra 0 · 0 =
1 + 1 =
1 · 1 =1 1
0 + 0 =
0 · 1 = 1 · 0 =
1 + 0 = 0 + 1 =
1 + 0 = 0 + 1 =
if x = 0 then x’ =
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if x = 1 then x’ =
Single-Variable Theorems x · 0 =
x + 1 =
1 x · 1 =
x + 0 =
x · x =
x + x =
x · x’ =
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x + x’ =
(x’)’ =
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Properties of Boolean Algebra Commutative
x · y =
+ x + y =
Associative
x · (y · z) =
x + (y + z) =
Distributive
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x · (y + z ) =
x + y · z =
Properties of Boolean Algebra
Absorptionx + x · y =
x · (x + y) =
Combiningx · y + x · y’ =
(x + y) · (x + y’) =
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Properties of Boolean Algebra
De Morgan’s Laws (x · y)’ =
(x + y)’ =
Otherx + x’·y =
x · (x’ + y) =
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Logic MinimizationA B C Y
0 0 0 0
Example
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
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1 0 1 0
1 1 0 1
1 1 1 0
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Recommended exercisesCombinational circuits
Ex 3.5, 3.6, 3.7, 3.8, 3.9
E 3 11 3 12 3 18 Ex 3.11, 3.12, 3.18
Ex 3.20, 3.22, 3.23, 3.24 with TA/Tut
Ex 3.30, 3.31, 3.35
Ex 3.44
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Building functions from logic gates Combinational Logic Circuit
Output depends only on the current inputs
Stateless (memoryless) Stateless (memoryless)
Sequential Logic Circuit Output depends on the sequence of inputs (past
and present)
Stores information (state) from past inputs
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Combinational vs. SequentialTwo types of “combination” locks
4 1 8 430
15
5
1020
25
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CombinationalSuccess depends only onthe values, not the order in which they are set.
SequentialSuccess depends onthe sequence of values(e.g, R-13, L-22, R-3).
Combinational vs. Sequential Combinational circuit
Always gives the same output for a given set of inputsinputs
Example: Adder always generates sum and carry, regardless of previous inputs
Sequential circuit Remembers previous input
Output depends on state and input
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Output depends on state and input
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Sequential Circuits Store information
Output depends on stored information (state) plus inputinput
So a given input might produce different outputs, depending on the stored information
Example: ticket counter
Advances when you push the button
Output depends on previous state
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Output depends on previous state
Useful for building memory elements and state machines
Feedback and Memory What if…
You connected an OR gate back to itself?
You connected an AND gate back to itself? You connected an AND gate back to itself?
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The Set Latch: Set Once
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The Reset Latch: Reset Once
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Set-Reset (SR) Latch Two inputs: Set and Reset
Start with both inputs at 1 (memory)
S t t 0 f th t i t t ti t t Set to 0 one of the two inputs at a time to store a value
The transition 00 → 11 generates an undefined output
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Set-Reset (SR) Latch
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D-Latch D-latch (D for data) is a
gated RS latch
Two inputs: D (data) and WE (write enable)
D QD QD QD Q
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Q
E
D Q
WE
Ck
Q
E
D Q
WE
Ck
D-Latch: Timing Diagram
0
1
time
CkD QD Q
time
0
1
time
WE
0
1
time
D
EWE
Ck
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time
0
1
time
Q
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D-Flip-Flop Two D-latches hooked
together
Connect one latch to the inverted clock
D-flip-flop is edge-triggered (changes only on the edge of the clock)
Also called “edge-triggered d-latch”
D QD QD QD QD Q
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gg
EWE
Ck
EEWE
Ck
D-Flip Flop: Timing Diagram
0
1
time
Ck
time
0
1
time
WE
0
1
time
D
D Q
E
D Q
WE
Ck
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time
0
1
time
Q
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D-Flip Flops in a Pipeline
0
1
time
Ck
time
0
1
time
WE
0
1
time
D
Q
D Q
E
D
WE
Ck
D Q
E
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time
0
1
time
Q
Q
Register A register stores a multi-bit value
Common WE which latches the n-bit value
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MemoryNow that we know how to store bits,we can build a memory – a logical k × m array of stored bits.
••
k = 2n
locations
Address Space:number of locations(usually a power of 2)
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••
m bits
Addressability:number of bits per location(e.g., byte-addressable)
22 x 3 Memoryword select word WE
address
write
input bits
enable
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addressdecoder
output bits
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State Machine
The basic type of sequential circuitCombines combinational logic with storage
“Remembers” state, and changes output (and state) based on inputs and current state
State Machine
CombinationalInputs Outputs
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CombinationalLogic Circuit
StorageElements
p p
Example of sequential machine
A 2-bit counter:
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Representing Multi-bit ValuesNumber bits from right (0) to left (n-1)
just a convention -- could be left to right, but must be consistent
Use brackets to denote range:D[l:r] denotes bit l to bit r, from left to right
A = 0101001101010101015
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A[2:0] = 101A[14:9] = 101001
May also see A<14:9>, especially in hardware block diagrams.
An LC-3 architecture’s sneak preview
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