Design of Binary Arithmetic Circuits

Experiment 7

Lab Report Comments:

Circuit Diagrams: Circuit Diagrams: ALWAYS INCLUDE !ALWAYS INCLUDE !– Titled Titled with a descriptive name for the circuitwith a descriptive name for the circuit– BriefBrief verbal description of verbal description of the circuit'sthe circuit's function / function /

purpose (what does it do?)purpose (what does it do?)– Circuit schematicCircuit schematic and/or and/or block diagramblock diagram

• Include Include all input/output signalsall input/output signals– When circuits are implemented in VHDL, When circuits are implemented in VHDL, signal names on signal names on

schematics should match signal names used in your VHDLschematics should match signal names used in your VHDL code code

• Include all input/output signals Include all input/output signals sources / destinationssources / destinations on the on the Development Board (switches, LEDs, etc.)Development Board (switches, LEDs, etc.)

• If combining multiple modules, show each module and the If combining multiple modules, show each module and the interconnectionsinterconnections– Not just 1 big “black box” for the whole thing.Not just 1 big “black box” for the whole thing.

Modular Design & Design Reuse

• Best to “reuse” a previously-designed, tested, verified VHDL module with as little change as possible – …or NONE, if possible!– Changes negate the benefits of having a

“proven, working” design• Ex: Rewriting the BCD-7seg in Exp 6 to use only 3-bit inputs

(to match Priority Enc output) was not the “best” solution

• This week, we will use a more powerful implementation of “Modular Design”……..

VHDL Structural ModelingVHDL Structural Modeling

VHDL Structural Modeling

• Reflects modern digital circuit design practice

• Supports preferred digital design approach

Hierarchical (Top-Down) Design

VHDL Structural Modeling Hierarchical (Top-Down) Design

Digital Alarm System

BCD-7 Seg Decoder

Priority Encoder4-bit Digital Comparator

AlarmController FSM

AND_2(AND gate)

NOR_2(NOR gate)

1-bit Digital Comparator

D Flip-Flop

(This is an Example of Multi-level Hierarchical Design. It is NOT necessarily how YOU should complete Exp 9.)

VHDL Structural Modeling

• Reflects modern digital circuit design practice

• Supports preferred digital design approach:

Hierarchical (Top-Down) Design

• Leverages software design techniques

• Supports readability, understandability, and reuse of code

• Allows for easy scalability of design

• Allows for the use of library-based modules

Instructional Objectives:

• To use concurrent VHDL statements in the design To use concurrent VHDL statements in the design of arithmetic circuitsof arithmetic circuits– Half AdderHalf Adder– Full AdderFull Adder

• Use “Structural Modeling” in VHDLUse “Structural Modeling” in VHDL– 4-bit Ripple Carry Adder4-bit Ripple Carry Adder– Using Half Adder & Full Adder as “Components”Using Half Adder & Full Adder as “Components”– ““Top Module” in same “Project” as Half Adder & Full Top Module” in same “Project” as Half Adder & Full

AdderAdder• To design a 4-bit Comparator To design a 4-bit Comparator (need for Alarm System)(need for Alarm System)

– Any VHDL Model style (architecture) you likeAny VHDL Model style (architecture) you like• (Hint: Probably NOT structural!)(Hint: Probably NOT structural!)

1-Bit Binary AdditionTo Add Two Single-Bit Binary Numbers:

A0 B0 Sum

S0

Carry

COut

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

A0B0 A0B0

1-Bit Binary AdderHalf Adder

HalfAdder

Ai Bi

COi Si

A0 B0

S0

CO0

Multiple-Bit Binary AdditionAlternative Approach: Modular Design

Use same approach as manual computation• Apply the same basic binary addition rules at each bit position• Need to handle “Carry In” for higher bit position additions

Modular Approach• Design a 1-bit “Full Adder” for 2 numbers + Carry In• Reuse the design for each upper bit position

A3 A2 A1 A0

+ B3 B2 B1 B0

CO S3 CO2 S2 CO1 S1 CO0 S0

A3-0

+ B3-0_______________________

CO S3-0

CI1CI2CI3

Input Variables Outputs

A B CIn Carry COut Sum

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

1-Bit Binary Full Adder

To Add Two 1-Bit Binary Numbers w/Carry In : Input Variables Outputs

A B CIn Carry COut Sum

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 ? ?

1 0 1 ? ?

1 1 0 ? ?

1 1 1 ? ?

FullAdder

Ai Bi CIi

COi Si

A B

CI

S

CO

4- Bit Ripple-Carry Adder A3 A2 A1 A0

+ B3 B2 B1 B0

S3 S2 S1 S0

FullAdder

Ai Bi CIi

COi Si

A3 B3

CI3

S3

CO3

FullAdder

Ai Bi CIi

COi Si

A2 B2

CI2

S2

CO2

FullAdder

Ai Bi CIi

COi Si

A1 B1

CI1

S1

CO1

HalfAdder

Ai Bi

COi Si

A0 B0

S0

CO0

CI1CI2CI3

CO0CO1CO2

COut

VHDL Structural Modeling

Similar to higher level language programming

Example circuit

Structural VHDL Code

A F B

A F B

A F B

Code3Code2Code1Code0

EQI3I2I1 I0

Key Comparator

4 switches(access code)

I7I6I5 Y2I4 Y1I3 Y0I2I1 STROBEI0

Priority Encoder

4 switches(sensors)

Connectto ground

Break-in Armed

OFF/ON_L Alarm

B3 B2 AA-AGB1 CATHB0

7-Seg Decoder

Alarm Control

Digital Alarm System

Experiment 7 P3

Preset Secret Code

4-Bit Comparator

4-Bit Comparator

Given two 4-bit binary numbers, A and B, determine if they are equal.

Multiple solutions:– Subtract B from A and test for zero result– Use VHDL operators

• require special libraries

– Use XNOR gates to do a bitwise comparison

Experiment 7 Overview

P1: Design, test, and implement a Half Adder

P2: Design, test, and implement a Full Adder

P3: Design and implement a 4-bit Ripple Carry Adder Using Structural Modeling

- Behavioral Simulation

P4: Design and implement a 4-bit ComparatorSave for use in Experiment 9

4-bit sumOf A+B

Nexys Development Board

Carry outEQUAL

A B

Place & Route

Post-RouteSimulation

Behavioral Simulation

Design Verification Steps

• Is the basic logic correct?

• Does the design still work with the actual devices used (with prop. delays, etc.)?

An important step for “real world” designs!!

Testing Strategies

We want to create input signal “test vectors” that will:

• Verify all important functions of our designs are working properly

• Be THOROUGH…..– Cover as many functions / cases as possible

• …..AND be EFFICIENT– Use as few test cases (vectors) as possible

Testing StrategiesPossible Approaches:

1. Test ALL POSSIBLE input combinations (Truth Table)

– Thorough!!– Good approach if the number of inputs is small.

If not reasonable, then consider:

2. Targeted Functional Testing– What are the important functions to verify?– What is already proven? (reuse)...what is not?– What could have gone wrong in the design that I should

check for?– How can we test each issue as efficiently as possible?

If it ain’t too bad,…Why not???

Then,…

BRAINSTORM

Testing the Half & Full Adders

FullAdder

Ai Bi CIi

COi Si

A1 B1

CI1

S1

CO1

HalfAdder

Ai Bi

COi Si

A0 B0

S0

CO0

How would you suggest testing these two devices?What method / test vectors would you choose?

Testing the Ripple-Carry Adder

FullAdder

Ai Bi CIi

COi Si

CI3

S3

CO3

FullAdder

Ai Bi CIi

COi Si

A2 B2

CI2

S2

CO2

FullAdder

Ai Bi CIi

COi Si

A1 B1

CI1

S1

CO1

HalfAdder

Ai Bi

COi Si

A0 B0

S0

CO0

COut

A3 B3

How many input signals?

How many Test Vectors to test ALL CASES?

4 (A) + 4 (B) = 8

28 = 256

Good Luck!!

Testing the Ripple-Carry Adder

FullAdder

Ai Bi CIi

COi Si

CI3

S3

CO3

FullAdder

Ai Bi CIi

COi Si

A2 B2

CI2

S2

CO2

FullAdder

Ai Bi CIi

COi Si

A1 B1

CI1

S1

CO1

HalfAdder

Ai Bi

COi Si

A0 B0

S0

CO0

COut

A3 B3

If you’ve already proven that the Half Adder & Full Adder designs are OK,…• What other “features” of the RCA do you need to verify?• What “mistakes” could you have made in the structural design that you should check for?

4- Bit Comparator

A

B

4-bitDigital

Comparator= 1 : if A = B= 0 : if A \= B

4

4

EQUAL

Verification Testing of the

• How might we approach “efficiently” testing this device?