Post on 20-Jun-2018
Design for Testability 1
Design for Testability
• Testability Measurement• DFT Basics• DFT Techniques
– ad hoc– Scan design– Boundary scan
Design for Testability 2
Testability
• Controllability: The ability to set somecircuit nodes to a certain states or logicvalues.
• Observability: The ability to observe thestate or logic values of internal nodes.
Design for Testability 3
Usage of Testability Measures
• Speed up test generation• Improve the design testability• Guide the DFT insertion
Design for Testability 4
Testability Measurement
• TMEAS [Stephenson & Grason, 1976]• SCOAP [Goldstein, 1979]• TESTSCREEN [Kovijanic 1979]• CAMELOT [Bennetts et al., 1980]• VICTOR [Ratiu et al., 1982]
Design for Testability 5
SCOAP
• Sandia Controllability Observability AnalysisProgram.
• Using integers to reflect the difficulty of controllingand observing the internal nodes.
• Higher numbers indicate more difficult to control orobserve.
• Applicable to both combinational & sequentialcircuits.
Design for Testability 6
Measurement in SCOAP• For a node A:
CC0(A) : Combinational 0-controllability CC1(A) : Combinational 1-controllability
SC0(A) : Sequential 0-controllability SC1(A) : Sequential 1-controllability
CO(A) : Combinational observability SO(A) : Sequential observability
Design for Testability 7
Combinational Components in SCOAP
CC0(x) = CC0(A) + CC0(B) + 1;CC1(x) = min{CC1(A), CC1(B)} + 1.SC0(x) = SC0(A) + SC0(B) ;SC1(x) = min{SC1(A), SC1(B)}.
– CC implies the distance from PI– SC implies the number of time frames needed to provide a
0 or 1.
Ex:AB x
Design for Testability 8
Sequential Components in SCOAP
• CC0(Q) = min{CC0(R), CC1(R) + CC0(D) + CC0(C) +CC1(C)}
• CC1(Q) = CC1(R) + CC1(D) + CC0(C) + CC1(C)• SC0(Q) = min{SC0(R), SC1(R) + SC0(D) + SC0(C) +
SC1(C)} + 1• SC1(Q) = SC1(R) + SC1(D) + SC0(C) + SC1(C) + 1
Ex:D
CCLK
DR
Design for Testability 9
Observalibity in SCOAP
N
P
RQ
• CO(P) = CO(N) + CC1(Q) + CC1(R) + 1• SO(P) = SO(N) + SC1(Q) + SC1(R)
• CO(R) = CO(Q) + CC1(Q) + CC0(R)
• SO(R) = SO(Q) + SC1(Q) + SC0(R) +1D
CCLK
DR
Design for Testability 10
Initial States
• PI: CC0 = CC1 = SC0 = SC1 = 1• PO: CO = SO = 0• All other numbers are initially set to ∞
Design for Testability 11
Importance of Testability Measures
• They can guide the designers to improve thetestability of their circuits.
• Test generation algorithms using heuristicsusually apply some kind of testability measuresto their heuristic operations (e.g., in makingsearch decisions), which greatly speed up thetest generation process.
Design for Testability 12
Design for Testability (DFT)
• Test Costs:– Test Generation– Fault Simulation– Fault Location
• Test Difficulties:– Sequential > Combinational– Control Logic > Data Path
• Testability– Controllability– Observability
– Test Equipment– Test Application Time
– Random Logic > StructuredLogic
– Asynchronous >Synchronous
Design for Testability 13
Design for Testability (DFT)
• DFT techniques are design efforts specificallyemployed to ensure that a device in testable.
• In general, DFT is achieved by employing extraH/W.
⇒ Conflict between design engineers and test engineers.⇒ Balanced between amount of DFT and gain achieved.
• Examples:– DFT
⇒ Area & Logic complexity⇒ Yield⇒ For fixed fault coverage, defect level
– Therefore, DFT must guarantee to increase fault coverage.
Design for Testability 14
Benefits of DFT
• In general, DFT has the following benefits:– Fault coverage– Test generation (development) time– Test length– Test Memory hope– Test application time– Support a test hierarchy– Concurrent engineering– Reduce life-cycle costs
⇒ Pay less now and pay more later without DFT!
• Chips• Boards• Subsystems• Systems
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Design for Testability 15
Costs Associated with DFTs
• Pin Overhead• Area / Yield• Performance degradation• Design Time⇒ There is no free lunch !
Design for Testability 16
DFT Techniques
• ad hoc DFT technology• Scan-based design• Boundary Scan
Design for Testability 17
Ad hoc Techniques
• Test points• Initialization• Monostable multivibrators (one shot)• Oscillators and clocks• Counter / Shift registers• Partitioning large circuits• Logic redundancy• Break global feedback paths....
Design for Testability 18
Example of ad hoc Techniques
• Insert test point
MUX
T/N
Design for Testability 19
Test Points
• Rule : to enhance controllability and observabilityby inserting control points (cp) and observationpoints (op), respectively.
• Ex:
original circuit
testable circuit
can be done only for board
C2 ..
C2 ..C1
C1
Design for Testability 20
• Using a CP for 0-injection and an OP forobservability:
• 0/1 Injection:
Test Points (Cont.)
CPC2
C1OP
0-I
C2C1
0/1 I
CP1CP2
Design for Testability 21
Test Points (Cont.)
• Using a MUX
0 MUX1
C1C2
G
CP1
CP2
CP2=0 : normalCP2=1: G=1 if CP1=1 G=0 if CP2=0
Design for Testability 22
Test Points (Cont.)
• MultiplexingObservation Points:
• Demultiplexing andLatching ControlPoints:
0
1
2n-1
. . . . MUX Z
01
2n-1
. . . .DEMUXZ
CP0
CP 2n-1
. . . .
Design for Testability 23
Selection of CP
• Control, address and data bus lines on bus-structured designs.
• Enable/hold inputs to microprocessors.• Enable and Read/write inputs to memory.• Clock and preset/reset inputs to F/Fs, counters,
shift registers, etc.• Data select inputs to multiplexers and
demultiplexers.• Control lines on tri-state devices.
Design for Testability 24
Selection of OP
• Stem lines with high fanout.• Global feedback path• Redundant signal lines• Outputs of devices with many inputs, e.g., multiplexers and parity generators.• Outputs from state devices.• Address, control, data buses
Design for Testability 25
Initialization
• Rule: Design circuits to be easily initialized– Don’t disable preset and clear lines
PR
CLR
PR
CLR
PR
CLR
PR
CLR
not goodfor testing
PR
CLR
PR
CLR
VDD
VDD
PRVDD VDD
VDD(a) (b) (c) (d)
Design for Testability 26
Monostable Multivibrator,Oscillators and Clocks
• Rule: Disable internal one shot, OSC and clocks– inserting CP and/or OP while disabling these
devices• Example:
COSC
AB
... ...
OP
Design for Testability 27
Partitioning Counters and ShiftRegisters
• Rule: Partition into small units• Ex: Register
C DI
CK
DoR1
DI DoR2
X1=> X2=>
=>
=>
Y1 Y2
CK
CP/test clock
CP/data inhibit
C DI DoR1
CK
DI DoR2
CKOPCP/clock
inhibit
CP/data inhibit
CP/test data CP/test data
Before
After
Design for Testability 28
Partition of Large CombinationalCircuits
• Rule : To reduce test generation costs and/or testapplication time
AB
C
D
E
F G
C1 C2
m n
p
q
s
Design for Testability 29
s
s
AT1T2 B
C
C1 C2
F GE
C’
F’ G’
0 1 1 0MUX MUX
MUX
MUX
1
0
1
0
ss
A’D
T1 T2
001
010
Mode
normal
test C1test C2
If 2p+n + 2q+m < 2m+n then test time can be reduced
m n
s
p
q
Design for Testability 30
Logic Redundancy
Rule: Avoid or eliminate redundancy ckt.• Design errors• Undetectable faults• Invalidation of some tests• Bias fault coverage
Design for Testability 31
Global Feedback Paths
Rule: break global feedback
C C
breakcontrol
break control
Design for Testability 32
Scan System
C
R
PIPO
SI
C
R’
PI
SO
PO
Original design Modified circuit
Design for Testability 33
Full Serial Integrated Scan
Sequential ATPG Combinational ATPG
CK
k k
CX Z
mn
R
Y E
k k
CX Z
mn
Rs
Y E
Sout
SinN/TCK
ScannedNormal
Design for Testability 34
Isolated Serial Scan (Scan/set)
X Z
SoutSin
Rs
S
Design for Testability 35
Full Isolated Scan (Structured)
• Shadow register• Real-time test support• snapshot
CX Z
R’
Rs
Sin Sout
S’
Design for Testability 36
Random-Access Scan(Non serial-structured)
• High area overhead• Faster test
application: only bitchange
• Concept ofcrosscheck
C
Addressablestorage
elements
X decoder
YDecoder
E Y
X-address
Y-address
clocks and controls
X Z
Sout
SinSCK
Si
Design for Testability 37
Scan Cell Design
• Static / Dynamic• Single / Double stages• Latch / Flip-flop (Clocking Scheme)
Usually Two Operation Modes• Functional mode• Shift mode
Design for Testability 38
IBM LSSD Scan Cell
• Gate Level
Q2=L2
=Sout
D
CSi
A
Q1=L1
B
Functional mode : A=0, C and B activeTest(Shift) mode : C=0, A and B active
Design for Testability 39
IBM LSSD Scan Cell (Cont.)
• Switch / Inverter level
D
Si
C
A
Q1=L1
Q2=L2
=Sout
B
B
Design for Testability 40
LSSD Double-Latch Design
Y
X
SRL Z
L1 L2
L1 L2
L1 L2
y1
y2
yn
Y
Sout
Scan path
CA
Sin=IB
Combinational Network
N
Design for Testability 41
Normal mode:
Test mode:
C
B
A
B
Clocking Scheme of LSSD Double-Latch
Design for Testability 42
LSSD Single-Latch DesignSRL
Y2
X1
C1
Y1
X2
C2
N1
N2
e11
e1n
e21
e2m
y21
y2m
y11
y1n
Y1
Y2
Sout
Z1
Z2
L1
L1
L1
L1
L2
L2
L2
L2
BA Sin
Scan path
Design for Testability 43
Scan Design Costs
• Area overhead• Possible performance degradation• Extra pins• High test time• Extra clock control
Design for Testability 44
Advanced Scan Concepts
• Partial scan (P.S.)• Multiple test session (M.T.S.)• Multiple scan chains (M.S.C.)• Broadcast scan chains (B.S.C)
Area overhead same same or same
Performance Degradation same same same
Extra clock control same same same same
Method P.S. M.T.S. M.S.C. B.S.C.
Extra pins same same same or
Test application time or
Design for Testability 45
Partial Scan: Only a subset of allflip-flops are scanned
TestGenerationComplexity
Comb. T.G.
Sequ. T.G.
100
partial scanfull scan
%scan F/F’s
•Trade-off between–Area overhead–Test generation complexity
Design for Testability 46
• Basic idea:– Representing a circuit as a directed graph
G=(v,E)– Trying to break cycles and reducing sequential
depth
Partial Scan by Cheng & Agrawal(pp. 544-548, IEEE Trans. Computers, Apr. ‘90)
Design for Testability 47
Graph Representation
• Each flip-flop i => a vertex Vi
• Each combinational path from FFi to FFj
!an edge form Vi to Vj
Ex:
65421
3
21
3
4
56
Design for Testability 48
Graph Representation
Def: Distance between two vertices on a path = # ofvertices on that path
dist = 4
dist = 3
Design for Testability 49
Graph Representation
Def: sequential depth of a circuit = the distance ofthe longest path
Def: Cycle length = maximum # of vertices in a cycle
EX: dist = 6
1
3
4 5 6
cycle length = 3 c.l. = 1 c.l. = 2
Design for Testability 50
Analysis of Sequential Circuits
• Any sequential circuit can be divided into 3classes of subcircuits based on the directedgraph representation1. acyclic directed2. directed with only self loops3. directed with cycles of two or more vertices
Ex:1.
Design for Testability 51
Analysis of Sequential Circuits(Cont.)
2.
3.
Design for Testability 52
Experimental Results
• Experimental results show that– # of gates or # FF’s is not the dominant factor
for test generation complexity– Cycle length is the dominant factor– Sequential depth is minor
! To reduce test generation complexity, cycles oflength >= 2 should be eliminated
Design for Testability 53
Flip-Flop Selection Algorithm
• Identify all cycles• Repeat for each vertex count the frequency of appearance in the cycle list select the most frequently used vertex
remove all cycles containing the remove (selected) vertexuntil (cycle list is empty)
! This is a feedback vertex set problem, a well-known NP-complete problem, hence heuristic isused.
Design for Testability 54
Experimental Results(Cheng & Agrawal ‘90)PARTICAl SCAN FOR MULT4 (382 GATES, 15 FLIP-FLOPS)
CPU sec.No. Ofscan FFs
Max cyclelength
DepthTest gen. Fault sim.
Faultcov.
No. Oftest
Totalvector
0 4 13 75 5 98.01% 115 1155 1 6 8 2 99.68% 69 3456 1 4 8 2 99.68% 72 432
PARTICAl SCAN FOR CHIP-A (1112 GATES, 39 FLIP-FLOPS)
CPU sec.No. Ofscan FFs
Max cyclelength
DepthTest gen. Fault sim.
Faultcov.
No. Oftest
Totalvector
0 1 14 269 274 98.80% 868 8688 1 10 85 56 99.60% 529 4132
16 1 6 49 33 99.80% 387 6192
Design for Testability 55
Experimental Results(Cheng & Agrawal ‘90)
PARTICAl SCAN FOR CHIP-B (5294 GATES, 318 FLIP-FLOPS)CPU sec.No. Of
scan FFsMax cycle
lengthDepth
Test gen. Fault sim.Faultcov.
No. Oftest
Totalvector
0 40 43 11018* 2256 82.60% 948 94814 1 19 2946* 2986 97.90% 2607 3949836 1 10 2041* 2765 98.30% 2494 8978444 1 6 1207* 2526 97.80% 1741 7660487 1 4 643* 862 98.20% 842 7325487 1 4 2294 7961 98.43% 2536 220632
*20% sample of total faults used for test gen. and fault sim.
Design for Testability 56
Experimental Results (Cheng & Agrawal ‘90)
TEST GENERATION FOR SEQUENTIAL BENCHMARK CIRCUITS WITH PARTIAL SCAN
CircuitName
TotalNo.OfFFs
Scan FFsNo. %
No. oftest
Vector
Fault Coverage(%)Tested Redundant
Total
Tgen + FsimSec
(VAX 8650)s400 21 9 42.86 107 99.81 1.89 100.00 7s713 19 7 36.84 83 90.71 9.29 100.00 18s5378 179 32 17.89 2612 93.38 6.32 99.70 1253s9234 228 53 23.25 3458 43.23 55.80 99.04 6208
Design for Testability 57
The BALLAST Methodology(Rajesh Gupta, Rajiv Gupta, M.A.Breuer,
IEEE T-Computers, Apr.’90)• Scan storage elements are selected such that
remainder of the circuit has some desirable structure.• A complete test set can be obtained using
combinational ATPG.
T.G.Complexity
SequATPG
Comb.ATPG
BALLAST
100 FF’s% scanned
Design for Testability 58
Example
C1
R2 C2 R5
R1 C3 R4
C4
R6
R3
SO
SI
Fig.1
Design for Testability 59
Example (Cont.)
• Test procedure:– Scan in a test pattern to R3 and R6 .– Hold test pattern in R3, R6 for two clock cycles
such that test response appears in R5 and R4.– Load data (from R5, R4) to R6, R3 and shift out
Design for Testability 60
Circuit Model
• Register:– Collection of one or more FF’s driven by the same clock
signal and (if any) mode control signal.• Two types of registers:
– Load set L - the set of registers whose FF’s have noexplicit load enable control => always operate in LOADmode.
– Hold set H - two modes of operations : LOAD and HOLD.• In the previous example, R1, R2, R4, R5 belong to
LOAD set, and R3, R6 belong to Hold set H.
Design for Testability 61
Circuit Model (Cont.)
• Clouds– The combinational logic logic in a circuit S can be partitioned
into clouds, where each cloud is a maximum region ofconnected combinational logic such that its inputs are eitherPIS or outputs of FF’s and its outputs are either POS or inputsto FF’S.
• Ex– In Fig.1 each block of C1, C2 , C3 and C4 represents a cloud.
No two clouds can be directly connected together.Each FF ( in any register ) must receive data fromexactly one cloud and must feed exactly one cloud.
FF’s can be grouped into registers such that each registerreceivers data from exactly one cloud and feeds exactly onecloud.
Design for Testability 62
V: set of clouds.A: connections between clouds through registers.H: arcs in H A represents HOLD registers.w:A Z+ ( positive integers) defines the number of
FF’S in each register. w(a) represents the cost of converting
register a into a scan path register.
Topology graph G=( V, A, H, W)
U
Design for Testability 63
Example
R2 R5
C2
C3
C1
C4
R3
R1 R4
Design for Testability 64
B-structure• S: a synchronous sequential circuit with topology
graph G=( V, A, H, W).• S is said to be to a balanced sequential structure
(B-structure) if– G is acyclic.– v1,v2 V, all directed paths from v1 to v2 are of
equal length.– h H, if h is removed from G, the resulting graph is
disconnected.• When considering whether a circuit with scan
registers is a B-structure, the arcs correspondingto scan registers must be removed.
.
UUA
A
• Condition 3 means that the removed of in thescan path will disconnect the graph.
Design for Testability 65
Kernel :The circuit excluding thescan path
• Combinational equivalent of of a B-structure: the combinational circuit formed by replacingeach FF in every register in by a wire.
• Depth d of :the longest directed path in thetopology graph
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Design for Testability 66
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Examples:
Design for Testability 67
• Given an input pattern I applied to ,the single -pattern output of for I is defined as the steady -state output of when I is held constant and allregisters are operated in LOAD mode for at leastd clock cycles
• Given some fault f in ,if the single-patternoutputs for I of the good and faulty circuits aredifferent , then I is a single -pattern test for f
B - structures : (1) single -pattern testable (2)complete single - pattern test set can be derivedusing combinational test generation techniques
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Design for Testability 68
Outline of BALLAST
(1) Construct the topology graph G of the circuit(2) Select a minimal cost set of arcs R to be removed
from G such that the remaining topology graph isbalanced. let be the B - structure correspondingto the resulting topology graph
(3) Determine of . Using a combination ATPGto determine a complete test set T for
(4) Construct a scan path by appropriately orderingthe registers in R and connecting them so thatthey can both “shift” and “hold”
Later some “hold”can be released
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Design for Testability 69
Selection of Scan Registers
(1) Transform G=(V,A,H,W) into an a cyclic topologygraph by removing a set of “feedback” arcssuch that is minimized
(2) Transform into a balanced topology graphby removing a set of arcs such thatis minimized R= is the desired set ofregisters
• Both(1) , (2) are NP-complete. Refer to the paperfor a heuristic for (2)
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Design for Testability 70
Eliminate on HOLD mode of ScanRegisters
• By adding two dummy bits between the patternsto be scanned to and ,the HOLD mode canbe eliminated
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Design for Testability 71
HOLD control(for test)
HOLD control(inoriginal circuit) (a)
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SISO
(b)
Design for Testability 72
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Design for Testability 73
Test Procedure
(1) all scan registers in SHIFT mode for l clock cycle(2) Repeat N times
a. HOLD all scan registers , LOAD all other for dcycles
b. LOAD all scan registers for 1 clock cyclec. SHIFT out scan data
Design for Testability 74
Multiple Test Session
• # patterns: C1 :100, C2: 200 and C3: 300
20 bits 20 bits 20 bits
C1 C2 C3
20 bits 20 bits 20 bits
C1 C2 C3
Test Time= 60 *300=18,000 (cycles)
Test Time= 60 *100+40*100+20*100=12,000 (cycles)
Design for Testability 75
Multiple Scan Chains
• Reduce test application time• Usually test I/O will share the normal I/O
Flip-Flop
TDITDOTMSTCK
Boundary Scan Interface
Flip-Flop
Design for Testability 76
Broadcast Scan Chains-General Hardware Architecture
• Using a single data input to support multiple scanchains
CUT(1) CUT(2) CUT(k)
MISR
Scan Input
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Design for Testability 77
Virtual Circuits
• The inputs of CUTs are connected in a 1-to-1manner.
Example :
The whole virtual circuit is considered as onecircuit during ATPG.
The resulting test patterns can be shared by allCUTs.
CUT(1) CUT(2)
(b) random connection
1 2 3 4 5 1 2 3 4
CUT(1) CUT(2)
(a) i-to-i connection
1 2 3 4 5 1 2 3 4
Design for Testability 78
Experimental ResultsExperimental results for ISCAS’85
ISCAS'85 Experiment Single Multiple Method 1 Method 2
Test Efficiency (%) 100 100 100 100
# Test Patterns 130 130 195 177
Scan Chain Length 834 206 206 206
Test Generation Time(secs) 163.2 163.2 122.2 130.3
Test Application Cycles 108420 26780 40170 36462
Normalized TestApplication Cycles
4.05 1 1.50 1.36
1 0.25 0.37 0.34
Method 1: Combine all input 1’s, input 2’s, etc.Method 2: Distributed.
Design for Testability 79
Experimental Results (Cont.)Experimental results for ISCAS’89
FFs : Only FFs are combined.FFs & PIs : Both FFs and PIs are combined.
ISCAS'89 Experiment Single MultipleMethod 1 Method 2
FFs FFs & PIs FFs FFs & PIsTest Efficiency (%) 100 100 100 100 100 100
# Test Patterns 281 281 287 294 280 285Scan Chain Length 6587 1728 1728 1728 1728 1728
Test Generation Time(secs) 1293.9 1293.9 1802.0 1820.1 1893.7 1869.2Test Application Cycles 1850947 485568 495936 508032 483840 492480
Normalized TestApplication Cycles
3.81 1 1.02 1.05 0.99 1.011 0.26 0.27 0.27 0.26 0.27