Decoupling Methodology

Taylor Shull

Decoupling Capacitor Methodology

Applications Engineering ConsultantApplications Engineering Consultant

Signal & Power Integrity

Goal of the PDN & Decoupling

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COMMON DECOUPLING MISTAKES

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MISTAKES

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Decoupling Mistakes

� Using the IC Vendor recommendations

� Incorrect values

� Rule of thumb and guess work

Decoupling Mistakes

� Using the IC Vendor recommendations

� Incorrect values

� Rule of thumb and guess work

� The LRC of the board is not taken into account

not taken into account

� Every Plane is different

� Your responsible for knowing your plane parasitics

Improper DecouplingVoltage Budget

A SIMPLE DECOUPLING STRATEGY

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STRATEGY

Decoupling Methodology

� Develop your Power Budget— DC Drop requirements— Target Impedance— Noise Budgets

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� Develop and Analyze the stackup— Determine low & high frequency limits

– First SRF & Exit Frequency– VRM Cross-over point

— Locate power cavities

� Determine Capacitor’s— Quantities— Values— Locations

Power Integrity Process Efforts

� Decoupling Capacitor Analysis— Pre-analysis: 80%— Post-analysis: 20%— Board / Plane outline that are close in pre analysis

provide relatively accurate results— Since the cap quantities & values are needed in the

schematic, there is a lot of value for pre-analysis

� Noise Analysis— Pre-analysis: 60%— Post-analysis: 40%— The goal here is to find areas of the plane that may

become noisy or have excessive overshoot/undershoot

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become noisy or have excessive overshoot/undershoot— Noise analysis will not correlate to lab, don’t try to do it.

The goal is to ensure an overall quiet plane

� DC Drop— Pre-analysis: 20%— Post-analysis: 80%— DC Drop analysis exposes area’s of the plane that are

narrow or places where voltage drop is excessive. — Since it’s difficult to determine every little anti-pad and

exact plane shape initially, the best place for this process is after the planes have been routed

— Pre-analysis can help determine needs for high current trace widths, stitching via quantities and overall design insight

— Determine what the max drop is for every rail— There is a batch mode analysis that is rules driven

POWER BUDGETS

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POWER BUDGETS

Calculate all Power needs

� DC Drop:— All significant parts— Max current

– May be done holistically by

Power Budgets

Target Impedance Schedule

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– May be done holistically by part

— Max voltage drop— VRM’s— Voltage rail

� Decoupling & Noise (AC)— Voltage— Allowed ripple— Max Current— Target impedance

Voltage Net name Vo

0-9vcc 0.9 2 5% 22.5 1.8

1.8v 1.2 0.5 2.5% 60 0.6

5v 5 2 5% 125 10

0.9v 0.9 5 5% 9 4.5

Excel table

Target Impedance (Zt)

� Target Impedance is the first thing that must be calculated

� Understand the goals of the power plane (voltage

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� Understand the goals of the power plane (voltage rail)

Lowest Target Impedance to Highest

� The lowest target impedance will be the hardest to decouple

Location of the lower Zt in

Sort the Target Impedances

Target Impedance Schedule

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� Location of the lower Zt in the stack up is critical

� Start your focus with the lowest Zt and work your way up

Voltage Net name Vo

0-9vcc 0.9 2 5% 22.5 1.8

1.8v 1.2 0.5 2.5% 60 0.6

5v 5 2 5% 125 10

0.9v 0.9 5 5% 9 4.5

Excel table

STACKUP ANALYSIS AND DEVELOPMENT

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DEVELOPMENT

� Goal is to select the right amount and value of capacitors to bring the impedance profile below the target impedance.

� The area in green is the area that can be affected by decoupling capacitors

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capacitors

� IC impedances take over anywhere between 300MHz and above, depending on IC package type

� The VRM (power supply chip) take care of power at the lower frequencies

Power Integrity Stackup Process

1. Determine proper power cavity design & stackup order

2. Determine decoupling capacitor / PDN frequency limits (1st

Proper PDN

Stackup Design

Determine Target

Impedance

Determine Board

outline

Peak Current

Voltage

Allowed Voltage Ripple

Mock Design up in

HL-PI Linesim

Import PCB Board

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frequency limits (1st

3. Finalize stackup

Determine Plane

Pair Cavity height

Determine Plane

Pair locationSimulate bare

board Distribution

Impedance

Understand where

Board SRF is

Determine Plane

Area limits

Plane Pair &

Location Complete

Stackups: Start here

� Develop your stackup for— Power requirements— Signal Requirements— Mechanical

Requirements— Cost Requirements

0.5 mils, Er = 3.3

0.675 mils, TOP, Z0 = 83.5 ohms, w idth = 6 mils

10 mils, Er = 4.3

1.35 mils, VCC

10 mils, Er = 4.3

Layer Stackup

Design: Untitled.ffs, Designer: tshull.

HyperLynx LineSim V8.1

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— Cost Requirements

� Caution on re-using old stackups— New designs may

require new stackups

56.4 mils

10 mils, Er = 4.3

0.675 mils, InnerSignal1, Z0 = 65.3 ohms, w idth = 6 mils

10 mils, Er = 4.3

0.675 mils, InnerSignal2, Z0 = 65.3 ohms, w idth = 6 mils

10 mils, Er = 4.3

1.35 mils, GND

10 mils, Er = 4.3

0.675 mils, BOTTOM, Z0 = 83.5 ohms, w idth = 6 mils

0.5 mils, Er = 3.3

Stackups: Signal integrity

� Traces = target impedances

� Signal layers have symmetry

� Proper return paths near by

� Impedance planning for Differential pairs

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Differential pairs

� Via signal / paths analyzed

� Develop stackup:— Document the stackup in

Hyperlynx— Save .stk files for all to use

– Save in the modeling section

– Re-use and apply for all development

— Define all Dielectric constants

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Stackups: Power Integrity

� Calculate Power Budgets— Target Impedances (Zt)

identified— Lower Zt planes toward

the edges (top & Bottom)

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Bottom)

� Keep cavities close together— Cavity = pwr & gnd pair— Less than 4mill

� Analyze:— 1st SRF, board size &

Target Impedances

PDN High Frequency Limits of the plane

� The first SRF is the first major dip at the bottom of the “V”

� This is the pure board impedance profile at a point of reference (we used 4 points in the previous example)

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previous example)

� Capacitors cannot decouple above the first SRF (The board inductance takes over)

� The 1st SRF will change based on different locations, stackup & area

A Power Cavity Impedance Profile(z-parameter): freq vs. impedance

Build a Pre-Analysis board

� Pre PI Analysis basics— Enter the stackup details— Build out a rough estimate of

the voltage plane— Something close is great to

start with design

Hyperlynx

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� Hyperlynx— Analyze different layers vs.

Target Impedance— Understand cap locations— Find first SRF— Understand interplane

capacitance & size trade-offs— Build out outline of board— Construct plane area

Find 1st SRF of the PDN

� First Self Resonant Frequency will determine the max frequency that a plane-pair can be decoupled

— Defines the upper frequency limit— Defines the values of the high-freq capacitors— Determine the first

� Hyperlynx— Place down 2 to 6 IC’s as reference points— Place 2 of them nearby each other (where the

IC would be) for self and trans impedance values

— Analyze Decoupling– Pick the voltage plane & reference plane

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– Pick the voltage plane & reference plane– Enter your target impedance (or calculate it)– Select “Distributed” Analysis– Select all IC’s to be analyzed– Custom

– All boxes unchecked– This provides just a view of pure plane

impedance

– Save off the file as a name that makes sense

— Results should show the first SRF (z-parameter)

� Design— This sets up everything for proper Capacitor

selection

Adding in a VRM

� VRM’s are the IC’s that provide voltage to your plane

� Decoupling effects:— Reduce impedance profile

at lower frequencies— Defines what needs to

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— Defines what needs to happen at the lower frequency decoupling caps

� DC Drop— This is the source of your

Voltage at DC on this plane

� Hyperlynx: — Add in a VRM module to

your plane

VRM Effects to the Impedance Profile

� Hyperlynx— Add VRM— Simulate just bare

board w/ VRM— Distributed

analysis– No Caps

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VRM reduces the profile at lower frequencies

Decoupling limits and capacitor boundaries

Stackups: Vias & finalizing stackup

� Signal impedances

� Power plane placements

� Cavities defined

� Analyze: Via structures— Are signal via’s an issue

to delay or quality?— Are decoupling cap & IC

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— Are decoupling cap & IC vias too inductive?

— Stub Effects, backdrill, HDI, microvias, blind & buried

— Return path & stitching vias

� Can the stackup be manufactured?

DECOUPLING CAPACITOR DEVELOPMENT

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DEVELOPMENT

PI: Power Integrity Process

1. Determine decoupling caps1. Quantity2. Values3. Locations

(approx)

Review noise for

Decoupling

Capacitor

Development

Simulate PDN

LRC w/o Models

Add in Capacitors

Simulate for

Lumped and

Distributed

Impedance Capacitor Models

Plane SRF

Target PDN

Impedance

Determine Board

outline Mock Design up in

HL-PI Linesim

Import PCB Board

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2. Review noise for area’s the plane needs capacitors

Determine cap

Values &

Quantities

Determine Cap

Locations

Impedance

Profiles

Noise / Voltage

Budget

Analyze Noise for

additional Cap

locations

Decoupling

Planning

Complete

Capacitor Parts to

schematicsSchematics

Noise Analysis

Capacitor development needs

� Add Capacitors to reduce the board impedance profile— Different values

& Quantities will be utilized

— Higher freq caps need to be more localized to the

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localized to the power pins

— Lower freq caps can be located anywhere

� The caps, VRM & Board all define the Power Distribution Network (PDN)

Differences in Capacitor Models

� 4 identical values & mounting— 0.1uf— ESL’s were all a little

different— Pick a model that

doesn’t have mounting ESL (or one that has just intrinsic ESL)

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just intrinsic ESL)

� Red & Purple (C1 & C2)— Hyperlynx Calculated

ESL’s (intrinsic)

� Green (C3)— 00603, Supposed to

only have intrinsic ESL values

� Yellow (C4)— 0603

– Note double dip

Capacitor Mounting

� Capacitor mounting will affect your ESL, and overall, your frequency response of your capacitor

� Analyzing basic mounting structures in Linesim is worth doing— Don’t over do it— Look for best design practices

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— Look for best design practices— Look for top or bottom based

mounting— Use the mounting editor for a

better understanding of complex mounting schemes

— You may stitch all grounds together here

— Explore via to via width, via size, etc

� Use ESL calculator for guidelines on cap mounting location

Capacitor Mounting Effects

� Mounting (or any other type of inductance) will shift the waveform left

� Red line is generic capacitors (no board or

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board or mounting effects)

� Purple line is the same caps with their mounting inductances included.

PI: Adding decoupling caps

� The Approach— Start with small sets

– Higher frequencies will require more caps

– Lower Frequencies will require less caps

– Target Impedance will determine how many and what quantities

— Don’t select caps that go

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— Don’t select caps that go above the 1st SRF frequency

— Take mounting into effect— Place small arrays (10 at a

time?)

� Place caps in small groups— Copy and place groups to

quickly add more.

� Analyze in Lumped analysis— Note the new SRF follows the

calculated resonance of the caps we selected

PI: Shaping the PDN Impedance Profile

� Yellow: Bare board Profile— Simulated in

Distributed

� Target Zo: 90 mohms

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� Red: Added 10x15nf caps— Simulated lumped

� Green: Added 10x1uf caps (Meets Target Impedance!)— Simulated lumped

PI: Shaping the PDN Impedance Profile

� Surround the IC pins with the caps

� Simulate Distributed— Look at the trans-

impedance (from one pin to another); preferable pins that are close together

— Profile looks good

Surround IC’s with caps

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together— Profile looks good— Check Exit frequency— Check Decoupling cap

mounting

� Optimization— Could get by with less 1uf

caps— Could try a few more

higher freq caps

Dist analysis trans impedance

Capacitor Mounting (Green) effects

DECOUPLING CAPACITOR DEVELOPMENT REVIEW

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DEVELOPMENT REVIEW

Decoupling Methodology

� Develop your Power Budget— DC Drop requirements— Target Impedance— Noise Budgets

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� Develop and Analyze the stackup— Determine low & high frequency limits

– First SRF & Exit Frequency– VRM Cross-over point

— Locate power cavities

� Determine Capacitor— Quantities— Values— Locations

Thank you

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Decoupling Methodology

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