Post on 06-Apr-2018
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Data communication
Chapter 6Chapter 6
Digital Data Communications TechniquesDigital Data Communications Techniques
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Data communication tasks
For two devices linked by transmission mediumto exchange data this task requires a grate dealof cooperation and agreement between the two
devices including:Synchronization.Error detection.
Error correction.
Interfacing.
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Asynchronous and Synchronous
Transmission
timing problems require a mechanism tosynchronize the transmitter and receiver
receiver samples stream at bit intervals
if clocks not aligned and drifting it will sample atwrong time after sufficient bits are sent
two solutions to synchronization problem
asynchronous transmission
synchronous transmission
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Asynchronous
Data transmitted on character at a time
5 to 8 bits
Timing only needs to be maintained within each
character Resynchronize with each character
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Asynchronous Transmission
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Asynchronous - Behavior
Example: Timing error
R=10kbps (T=100 micro)
Rx is fast by 6%
The 8th
bit in errorIf bit 7 is 1 and bit 8 is 0, bit 8 is start bit framing
error
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Asynchronous - Behavior
In a steady stream, interval between charactersis uniform (length of stop element)
In idle state, receiver looks for transition 1 to 0
Then samples next seven intervals (char length) Then looks for next 1 to 0 for next char
Simple
Cheap Overhead of 2 or 3 bits per char (~20%)
Good for data with large gaps (keyboard)
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Synchronous - Bit Level
Block of data transmitted without start and stopbits
Clocks in TX and RX must be synchronized
Can use either separate clock lineGood over short distances
Subject to impairments
or embed clock signal in data by proper
encoding methodManchester/differential manch. encoding (digital)
Carrier frequency (analog)
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Synchronous - Block Level
Need to indicate start and end of block
Use preamble and postamble bit pattern.
Data block+preample+postamble+control
data=frame. More efficient (lower overhead) than async.
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Synchronous frame format
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Types of Error
An error occurs when a bit is altered betweentransmission and reception
Single bit errors One bit altered
Adjacent bits not affected White noise
Burst errors Length B
Contiguous sequence of B bits in which first and last bits and
any number of intermediate bits are in error. Impulse noise
Fading in wireless
Effect greater at higher data rates.
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Error Detection
Always there will be errors
Detect errors using error-detecting code
added by transmitter
error-detecting code Recalculated and checkedby receiver
still chance of undetected error despite usingerror-detecting code.
parityparity bit set so character has even (even parity) or
odd (odd parity) number of ones
even number of bit errors goes undetected
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Error Detection Process
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Error detection
Horizontal and Vertical parity
A variation of parity scheme
Parity bits are added in both dimensions
Horizontal
Vertical
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Cyclic Redundancy Check (CRC)
For a block of k bits (D ) transmitter generates (n-k) bitsequence (R: frame check seq. FCS)
Transmit n bits (T ) which is exactly divisible by somenumber P of length (n-k+1). i.e
Receive divides the received frame by P
If no remainder, assume no error. i.e
2n kT D R!
2n kDQ R
p
!
rT
or equivalentlyr
r
E T T
T T E
!
!
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ErrorCorrection
correction of detected errors usually requires data blockto be retransmitted
not appropriate for wireless applications bit error rate is high causing lots of retransmissions
when propagation delay long (satellite) compared with frametransmission time, resulting in retransmission of frame in errorplus many subsequent frames
instead need to correct errors on basis of bits received
error correction provides this
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CRC
Polynomial representation
Number the bits 0, 1, ...,n from right, considerthese as coefficients of a polynomial P(x)
Example
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Error detection
CRC generation
4 5 6 8
3
( )
( ) 1
( ) 1
T x x x x x
P x x
R x x
!
!
!
p
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Error detection
How CRCs detect errors?
When there are errors, is received
Each 1 bit in is an inverted bit
When the receiver calculates the remainder R[(T(x) + E(x) )/p(x)]
because R[T(x )/p(x)] = 0, the result is R[E(x) /p(x)] Thus if p(x) divides E(x) then errors go undetected!
Consider a 1-bit error,
i is the bit in error If p(x) contains more than two terms it never divides E(x)
Thus CRC with p(x) that has more than two terms will catch all 1bit errors
( ) ( )T x E x
( )E x
( )j
E x x!
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Error detection
How CRCs detect errors?
Lets consider two isolated single bit errors
If does not divide up to max frame length, CRCs
will catch all double errors For example: will not divide xk+1 up to
k=32,768, thus CRCs based on this polynomial candetect all double errors for frames up to 32,768 bits long
( ) wherei jE x x x i j! "-( ) ( 1)j i jE x x x!
kx +1( )p x
15 14( ) 1 p x x x!
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Error detection
Feature ofCRCs
CRCs used in standards
CRC-12 =
CRC-16 =
CRC-CCITT =
The last two (16 bits CRCs) will detect all single and double errors
all errors with odd number of bits
all burst errors of length 16 bits or less
99.997% of all 17 bit errors
99.998% of all 18-bit or longer bursts
12 11 3 2 1 x x x x x 16 15 2 1 x x x 16 12 5
1 x x x
( )p x
( )p x
( )p x
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Error detection
Use ofCRC codes
CRC codes are the most common errordetection scheme used in data transmission
Less overhead yet more robust than parityand check sum
Detection capabilities depends on p(x)
selection
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Error control
Hamming Codes
Code word
consists of m message bits + r redundant or checkbits
Code word length: n = r + m
Hamming distance
The number of bit positions at which two codewords differ Can be obtained by XORing two codewords
Example: 0110000 and 0010111 (4)
Why Hamming distance is important?
If two codewordss Hamming distance is d, it takes d single bit errorsto convert one to another
Look differently, if received code word and transmitted code hasHamming distance of d, d single bit-errors have occurred
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Error correcting codes
Hamming Codes
To detect d single-bit errorswe need hamming code C of a minimum Hamming
distance d+1
because there is no way d single bit errors can change
one valid codeword into another valid code word To correct d single-bit errors
we need a Hamming distance 2d+1
because valid codewords are so far apart so that with
even d single single-bit changes, the original codewordand the modified codeword are still closest
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Error control
Error correcting codes
Contain enough information to self-corrected transmissionerrors
For example, H & V parity check can correct one single bit error
Codewords with Hamming distance 2d+1 can correct d
single-bit errors bit errors Not used much in data transmission due to rather large
overhead Used only when transmission costs are expensive
Used in computer memory
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Error control
Error correcting example
Example:
Code words 0000000000
1111100000
0000011111 1111111111
What is Hamming distance of this code?
How many bit errors this code can correct? If we receive 0000000111, what is the correct code?
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Line Configuration
Topology
Physical arrangement of stations on transmission medium
Point to point
Multi point
Computer and terminals, local area network Half duplex
Only one station may transmit at a time
Requires one data path
Full duplex
Simultaneous transmission and reception between two stations
Requires two data paths (or echo canceling)
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Traditional Configurations
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Interfacing
Data processing devices (or data terminalequipment, DTE) do not (usually) include datatransmission facilities
Need an interface called data circuit terminating
equipment (DCE)e.g. modem, NIC
DCE transmits bits on medium
DCE communicates data and control info withDTEDone over interchange circuits
Clear interface standards required
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Data Communications
Interfacing
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Characteristics ofInterface
Mechanical
Connection plugs
Electrical
Voltage, timing, encoding Functional
Data, control, timing, grounding
Procedural
Sequence of events
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V.24/EIA-232-F
ITU-T v.24
Only specifies functional and procedural
References other standards for electrical and
mechanical EIA-232-F (USA)
RS-232
Mechanical ISO 2110
Electrical v.28Functional v.24
Procedural v.24
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Mechanical Specification
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Functional Specification
Circuits grouped in categories
Data
Control
TimingGround
One circuit in each direction
Full duplex
Two secondary data circuitsAllow halt or flow control in half duplex operation
(See table in Stallings chapter 6)
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Procedural Specification
E.g. Asynchronous private line modem
When turned on and ready, modem (DCE) asserts DCEready
When DTE ready to send data, it asserts Request to
SendAlso inhibits receive mode in half duplex
Modem responds when ready by asserting Clear to send
DTE sends data
When data arrives, local modem asserts Receive LineSignal Detector and delivers data
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Dial Up Operation (1)
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Dial Up Operation (3)
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Null Modem
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ISDN Physical Interface Diagram
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ISDN Physical Interface
Connection between terminal equipment (c.f.DTE) and network terminating equipment (c.f.DCE)
ISO 8877 Cables terminate in matching connectors with 8
contacts
Transmit/receive carry both data and control
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ISDN Electrical Specification
Balanced transmission Carried on two lines, e.g. twisted pair
Signals as currents down one conductor and up the other
Differential signaling
Value depends on direction of voltage Tolerates more noise and generates less
(Unbalanced, e.g. RS-232 uses single signal line and ground)
Data encoding depends on data rate
Basic rate 192kbps uses pseudoternary
Primary rate uses alternative mark inversion (AMI) and B8ZS orHDB3