Custom Single PurposeProcessors: Hardware

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Outline

Introduction Combinational logic Sequential logic Custom single-purpose processor design RT-level custom single-purpose processor design

Chapter 2: Custom single-purpose processors

Digital Foundations

The basic model of a computer system:

CPU MEM

I/O

Central Processing Unit (CPU)

CPU MEM

I/O

Memory

CPU MEM

I/O

Input/Output (I/O)

CPU MEM

I/O

Hierarchical View of EP and Digital Systems

CPU MEM

I/O

GatesBoolean Algebra

Design Techniques

MSI Functions

State Machines

Interface Method

Computer Architecture

Operating System

HLLs

Introduction

Processor Digital circuit that performs a computation

tasks Controller and datapath General-purpose: variety of computation

tasks Single-purpose: one particular computation

task Custom single-purpose: non-standard task

A custom single-purpose processor may be Fast, small, low power But, high NRE, longer time-to-market, less

flexible

Microcontroller

CCD preprocessor

Pixel coprocessorA2D

D2A

JPEG codec

DMA controller

Memory controller ISA bus interface UART LCD ctrl

Display ctrl

Multiplier/Accum

Digital camera chip

lens

CCD

CMOS transistor on silicon

Transistor The basic electrical component in digital systems Acts as an on/off switch Voltage at “gate” controls whether current flows from source to

drain Don’t confuse this “gate” with a logic gate

source drainoxidegate

IC package IC channel

Silicon substrate

gate

source

drain

Conductsif gate=1

1

CMOS transistor implementations

Complementary Metal Oxide Semiconductor

We refer to logic levels Typically 0 is 0V, 1 is 5V

Two basic CMOS types nMOS conducts if gate=1 pMOS conducts if gate=0 Hence “complementary”

Basic gates Inverter, NAND, NOR

gate

source

drain

nMOS

Conductsif gate=1

gate

source

drain

pMOS

Conductsif gate=0

Basic logic gates

F = x yAND

F = (x y)’NAND

F = x yXOR

F = xDriver

F = x’Inverter

x F

F = x + yOR

F = (x+y)’NOR

x F

x

yF

Fx

y

x

yF

x

yF

x

yF

F = x yXNOR

Fyxx

0y0

F0

0 1 01 0 01 1 1

x0

y0

F0

0 1 11 0 11 1 1

x0

y0

F0

0 1 11 0 11 1 0

x0

y0

F1

0 1 01 0 01 1 1

x0

y0

F1

0 1 11 0 11 1 0

x0

y0

F1

0 1 01 0 01 1 0

x F0 01 1

x F0 11 0

Combinational logic designSummary

A) Problem description

y is 1 if a is to 1, or b and c are 1. z is 1 if b or c is to 1, but not both, or if all are 1.

D) Minimized output equations

00

0

1

01 11 10abcy

y =

00

0

1

01 11 10z

z =

abc

C) Output equations

y=

z =

B) Truth table

1 0 11 1 01 1 1

0 0 10 1 00 1 11 0 0

0 0 0

Inputsa b c

Outputsy

E) Logic Gates

abc

y

z

z

RT LevelCombinational components

With enable input e all O’s are 0 if e=0

With carry-in input Ci

sum = A + B + Ci

May have status outputs carry, zero, etc.

O =I0 if S=0..00I1 if S=0..01…I(m-1) if S=1..11

O0 =1 if I=0..00O1 =1 if I=0..01…O(n-1) =1 if I=1..11

sum = A+B (first n bits)carry = (n+1)’th bit of A+B

less = 1 if A<B equal =1 if A=Bgreater=1 if A>B

O = A op Bop determinedby S.

n-bit, m x 1 Multiplexer

O

…S0

S(log m)

n

n

I(m-1) I1 I0

…

log n x n Decoder

…

O1 O0O(n-1)

I0I(log n -1)

…

n-bitAdder

n

A B

n

sumcarry

n-bitComparator

n n

A B

less equal greater

n bit, m function

ALU

n n

A B

…S0

S(log m)

n

O

Multiplexer Decoder Adder Comparator ALU

Sequential Circuits

Include feedback Presence of a clock Behavior is no longer simply a function of the inputs--

must be evaluated synchronously with clock Flip-flops

D-type J-K type S-R type etc.

CK

QD

D-F/F

Excitation Function: Dn = Qn+1

Q*

P

C

P C Dn Qn+1

1

0 1 X

1 1 1

1 0 X

1 1 0

0 0 X

1

0

Illegal0

State Machines

Mealy: Outputs depend on states and on inputs. Moore: Outputs depend only on states. One-Hot: A type of Moore machine in which there is one F/F per

state.

State Machine Models

(& One-Hot)

Inputs

State Memory

Combinatorial Network

Clk

Moore Outputs

Mealy Outputs

Sequential Circuit Design

Problem statement State diagram Transition table Simplified excitation functions Implementation Verification

Example

Design a sequence detector that will identify 1011.

SM1011 Z

State Diagram

Input

Input

Input/Output

Input/Output

Name

OutputName

Moore Mealy

One-Hot SMs

Moore machines are glitchless since outputs change only synchronously with clock.

For relatively small numbers of states, techniques of F/F minimization are largely counterproductive with available “sea-of-gates” FPGA. A 12-state SM: Don’t bother to reduce/encode. A 16-bit counter: Definitely encode states.

SM for 1011 Sequence Detector

Reset

Found1

Found2

Found3

Found4

Z

Found

None

1

0

0

11

1

0

0

0

1

Note: Dashed lines show non-resetting algorithm.

Transition Table

Output Present State Input Next State

Z F0 F1 F2 F3 F4 X F0’ F1’ F2’ F3’ F4’ 0 1 0 0 0 0 0 1 0 0 0 0

1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 0 0

Excitation Functions

The Transition Table could be large: 26 = 64, but since this is a One-Hot SM, there can be only one state active at a time. When writing the BA for each excitation function, listing the complemented states is redundant.

For example: DF0 = F0•X* + F2•X*, instead of

DF0 = F0•F1*•F2*•F3*•F4*•X* + F0*•F1*•F2•F3*•F4*• X*

Similarly,

DF1 = F0•X + F1•X + F4•X

DF2 = F1•X* + F3•X* + F4•X*

DF3 = …..

DF4 = …….

Simplification

If there are any redundant terms, we can simplify; however, for One-Hot approach, there are no simplifications possible since we must account for every separate state path using a separate FF.

Implementation

Assign one D-F/F per state and complete the combinatorial network required for each input. Implementation of F0 is shown:

The final network output, Z = F4. For reset, use asynchronous F/F inputs: Preset F0 and clear F1-F4.

Clk

&

&+ D Q F0

F0

F2

X*

X*

P

Verification

Check that the SM performs as required.More complex input vectors are required since the internal

state memory expands total possible states.Use simulation tools.

The Power of One-Hot Design

Can skip transition table--“read” the implementation directly off the state diagram:

Found11

1

Found

None

Clk

&

&+ D Q F1

F0

F1

X

X C

Sequential Circuit Functions

Counters Binary, BCD Ripple, Synchronous

Registers and Latches PIPO, PISO, SIPO, SISO

Sequential components

Q = 0 if clear=1, I if load=1 and clock=1, Q(previous) otherwise.

Q = 0 if clear=1, Q(prev)+1 if count=1 and clock=1.

clear

n-bitRegister

n

n

load

I

Q

shift

I Q

n-bitShift register

n-bitCounter

n

Q

Q = lsb - Content shifted - I stored in msb

clear

count

Sequential logic designSummary

A) Problem Description

You want to construct a clock divider. Slow down your pre-existing clock so that you output a 1 for every four clock cycles

Sequential logic design (cont.)

E) Minimized Output Equations F) Combinational Logic

a

Q1 Q0

I0

I1

x