CS 105DIGITAL LOGIC

DESIGN

Chapter 4Combinational

Logic

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Outline

4.1 Introduction. 4.2 Combinational Circuits. 4.3 Analysis Procedure. 4.4 Design Procedure. 4.5 Binary Adder-Subtractor. 4.6 Decimal Adder. 4.7 Binary Multiplier. 4.9 Decoders. 4.10 Encoders. 4.11 Multiplexers.

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4.1 Introduction (1-2)

Logic circuits for digital systems may be combinational or sequential.

Consists of logic gates whose outputs at any time are determined from only the present combination of inputs.

Performs an operation that can be specified logically by a set of Boolean functions.

Combinational Circuit

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4.1 Introduction (2-2)

Employs storage elements in addition to logic gates.

Their outputs are a function of the inputs and the state of the storage elements.

Because the state of the storage elements is a function of previous inputs, the outputs of a sequential circuit depend not only on present value of inputs, but also on past inputs.

Sequential Circuit

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4.2 Combinational Circuit (1-2)

Input Variables

Consists of: Logic Gates

Output Variables

Transforms input data into required output data.

Combinational circuitsn inputs m outputs.

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.

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Block diagram

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4.2 Combinational Circuit (2-2)

n input variables 2n binary input combinations. Each possible combination one possible

combination output. Combinational circuit can be specified with truth

table. Combinational circuit can be described by m

Boolean functions. Each output function is expressed in terms of

the n input variables.

Standard Combination Circuits

Adders, subtractors, comparators, decoders, encoders and multiplexers

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4.3 Analysis Procedure (1-4)

Determine the function that the circuit implements from a logic diagram.

Circuit’s function can be determined by either Boolean function or truth table.

Steps

Make sure that it is combinational not sequential. No memory elements. No feedback path (feedback path: a connection from

the output of one gate to the input of a second gate that forms part of the input to the first gate).

Obtain Boolean function or the truth table.

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4.3 Analysis Procedure (2-4)Boolean function

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4.3 Analysis Procedure (4-4)

Truth Table

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4.4 Design Procedure (1-7)

Steps

State the problem. From the specifications of the circuit, determine the

required number of inputs and outputs and assign a symbol to each.

Derive the truth table that defines the required relationship between inputs and outputs.

Obtain the simplified Boolean functions for each output as a function of the input variables.

Draw the logic diagram and verify the correctness of the design

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4.4 Design Procedure (2-7)

Example

Design a circuit that converts binary coded decimal (BCD) to the excess-3 code for the decimal digits.

InputsOutput

s BCD (4 bits). 4 inputs. Symbols: A, B, C, D.

Ex-3 (4 bits). 4 outputs. Symbols: w, x, y, z.

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4.4 Design Procedure (7-7)

Logic Diagram

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4-5 Binary Adder-Subtractor (1-20)

Binary Adder-Subtractor

Is a combinational circuit that performs the arithmetic operations of addition and subtraction with binary numbers.

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Half adder

Is a combinational circuit that performs the addition of two bits.

0 + 0 = 0 ; 0 + 1 = 1 ; 1 + 0 = 1 ; 1+ 1 = 10

Elementary Operations

Truth Table

two input variables x, y.

two output variables. C (output carry), S (least

significant bit of the sum).

4-5 Binary Adder-Subtractor (2-20)

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Half adder

S = x'y+xy' C = xy

Simplified Boolean Function (Sum of

Products)

Logic Diagram (Sum of

Products)

4-5 Binary Adder-Subtractor (3-20)

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Half adder

S=x Å yC = xy

Simplified Boolean Function (XOR and AND

gates)

Logic Diagram (XOR and AND

gates)

4-5 Binary Adder-Subtractor (4-20)

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Functional Block: Full-Adder

It is a combinational circuit that performs the arithmetic sum of three bits (two significant bits and previous carry).

It is similar to a half adder, but includes a carry-in bit from lower stages.

Two half adders can be employed to implement a full adder.

Inputs & Outputs Three input bits:

x, y : two significant bits Z : the carry bit from the previous lower significant bit.

Two output variables: C (output carry), S (least significant bit in sum).

4-5 Binary Adder-Subtractor (5-20)

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For a carry-in (Z) of 0, it is the same as the half-adder:

For a carry- in(Z) of 1:

Z 0 0 0 0X 0 0 1 1

+ Y + 0 + 1 + 0 + 1

C S 0 0 0 1 0 1 1 0

Z 1 1 1 1X 0 0 1 1

+ Y + 0 + 1 + 0 + 1

C S 0 1 1 0 1 0 1 1

Functional Block: Full-Adder

Operations

4-5 Binary Adder-Subtractor (6-20)

Add two BCD‘s: 9 inputs: two BCD's and one carry-in. 5 outputs: one BCD and one carry-out.

Design approaches Use unary full Adders. A truth table with 29 entries Each input digit does not exceed 9. The output sum connot be greater than 9.

e.g. 9 + 9 + 1 =19 , the 1 in sum being an input carry.

The output of the binay sum must be represented in BCD.

BCD Adder

4-6 Decimal Adder (1-4)

BCD AdderTruth Table

4-6 Decimal Adder (2-4)

BCD AdderLogic Diagram

4-6 Decimal Adder (4-4)

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Multiplication of binary numbers is performed in the same way of decimal numbers.

Example Consider the multiplication of two 2-bit numbers.

Multiplicand bits are B0 and B1.

Multiplier bits are A0 and A1.

The product is C3C2C1C0.

4-7 Binary Multiplier (1-4)

The partial product can be implemented with AND gates.

The two partial products are added with two half-adder (HA) circuits.

Logic Diagram

4-7 Binary Multiplier (2-4)

J-Bit by K-Bit Binary Multiplier For J multiplier bits and K multiplicand bits to produce J +

K bits , we need : J x K AND gates. (J-1) K-bit adders.

Example (4-Bit by 3-Bit Multiplier)

Multiplicand : B3B2B1B0

Multiplier: A2A1A0

12 AND gates 2 four-bit adders. Produces product of 7 bits

4-7 Binary Multiplier (3-4)

Example (4-Bit by 3-Bit Multiplier)

4-7 Binary Multiplier (4-4)

4-9 Decoder (1-16)

Discrete quantities of information are represented in digital systems by binary codes.

A binary code of n bits is capable of representing up to 2n distinct elements of coded information.

Is a combinational circuit that converts the binary information from n input lines to a maximum of 2n unique output lines.

If the n-bit coded information has unused combinations, the decoder may have fewer than 2n outputs.

Called n-to-m-line decode, where m <= 2n minterms of n input variables.

Decoder

4-9 Decoder (2-16)

Inputs = 3. Outputs = 8 (minterms)

ExampleConsider three-to-eight-line decoder

circuit

Truth Table

Example:Binary – to –

octal decoderONLY one output can be active at

any time

4-9 Decoder (3-16)Logic

Diagram

4-9 Decoder (4-16)

Generates decoder minterms in their complemented formNAND gates

4-9 Decoder (5-16)

A decoder with one or more enable (E) inputs. Control the circuit operation. E =0, Decoder is disabled. E =1, Decoder is enabled.

A circuit that receives information from a single Line and directs it to one of 2n possible output lines.

Demultiplixers

4-9 Decoder (6-16)

DemultiplixersDesign a two-to-four-line decoder with an enable

input.Truth table

D3 D2 D1 D0 B A E0 0 0 0 X X 00 0 0 1 0 0 10 0 1 0 1 0 10 1 0 0 0 1 11 0 0 0 1 1 1

Uncomplemented output

4-9 Decoder (7-16)

DemultiplixersDesign a two-to-four-line decoder with an enable

input.Logic Diagram

4-9 Decoder (8-16)

DemultiplixersDesign a two-to-four-line decoder with an enable

input constructed with NAND gates.

Truth table

D3 D2 D1 D0 B A E1 1 1 1 X X 11 1 1 0 0 0 01 1 0 1 1 0 01 0 1 1 0 1 00 1 1 1 1 1 0

Complemented output

4-9 Decoder (9-16)

Demultiplixers

Logic Diagram

Design a two-to-four-line decoder with an enable input constructed with NAND gates.

4-9 Decoder (10-16)

Demultiplixers

Design a 4-to-16 decoder.

Design a 4-to-16 decoder using two 3-to-8 decoders.

4-9 Decoder (12-16)

DemultiplixersDesign a 5-to-32 line decoder using four 3-to-8 line

decoders with enable inputs and a 2-to-4 line decoder.

D0 – D7

D8 – D15

D16 – D23

D24 – D31

A3

A4

A0

A1

A2

2-4-line Decoder

3-8-line Decoder

3-8-line Decoder

3-8-line Decoder

3-8-line Decoder

E

E

E

E

4-9 Decoder (13-16)

Combinational Logic Implementation

Each output = minterm. Implementing Boolean function (expressed in sum

of minterms) by using: A decoder . An external OR gate.

Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2n-line decoder and m OR gates.

4-9 Decoder (14-16)

Combinational Logic ImplementationDesign a full adder using a

decoder.

4-10 Encoder (1-7)

Is a digital circuit that performs the inverse operation of a decoder.

An encoder has 2n (or fewer) input lines and n output lines.

ExampleDesign an octal-binary

encoder

4-10 Encoder (2-7)

ExampleDesign an octal-binary

encoder

4-10 Encoder (3-7)

Limitations on previous example

If two inputs are active simultaneously, the output produces an undefined combination.• E.g. if D3 and D6 are 1 simultaneously, the output of

the encoder will be 111.• Resolve this ambiguity, establish an input priority

to ensure. D6 will be the higher priority. Output with all 0's is generated when:

• All the inputs are 0• D0 is equal to 1.• Resolve by providing one more output to indicate

whether at least one input is equal to 1.

4-10 Encoder (4-7)

Priority Encoder

Is an encoder circuit that includes the priority function.

Resolve the ambiguity of illegal inputs. if two or more inputs are equal o 1 at the same

time. the input having the highest priority will take precedence.

4-10 Encoder (5-7)

Priority EncoderDesign an four –to - two priority

encoder

4-11 Multiplexer (1-15)

is a combinational circuit that selects a binary information from one of many input lines and directs it to a single output line.

The selection of a particular input line is contro1led by a set of selection lines.• 2n input lines and n selection lines whose bit

combinations determine which input is selected.

Also called a data selector, since it selects one of many inputs and steers the binary information to the output line.

The size of a multiplexer is specified by the number 2n of its data input lines and the single output line.

4-11 Multiplexer (2-15)

ExampleDesign a 2 –to-1 line

MUX Data Inputs = 21=1 Selection Input= 1 Output = 1

Y S0

I0 0

I1 1

Function Table

4-11 Multiplexer (3-15)

ExampleDesign a 4 –to-1 line

MUX

Data Inputs = 22 =4

Selection Input= 2 Output = 1

Function Table

4-11 Multiplexer (4-15)

ExampleDesign a 4 –to-1 line

MUX

4-11 Multiplexer (5-15)

Notes 2n – to – 1 MUX can be implemented using

decoder:• Decode selection input lines.• n (selection input lines) – to - 2n decoder.• Adding the 2n input lines to each AND gate.• OR all AND gates.• An enable input (an option).

Multiplexers may have an enable input to control the operation of the unit• When the enable input is in the inactive state, the

outputs are disabled.• When it is in the active state, the circuit functions

as a normal multiplexer.

4-11 Multiplexer (6-15)

ExampleDesign an 8–to-1 line MUX using a 3-to-8 line

decoder.

4-11 Multiplexer (7-15)

Multiple bit Selection Multiplexer circuits can be combined with

common selection inputs to provide multiple-bit selection logic.

E.g. quadruple 2-to-1 line MUX.

4-11 Multiplexer (8-15)

Quadruple 2-to- 1 -line multiplexer.

4-11 Multiplexer (9-15)

Boolean Function Implementation Boolean function with n variables can be

implemented with a multiplexer that has:• n-1 selection inputs.• 2n-1 data inputs.

The first n-1 variables connected to the selection inputs of the MUX.

The remaining single variable of the function is used for the data inputs.• If the single variable is denoted by z ,

each data input of the MUX will be z,z’,1 or 0.

4-11 Multiplexer (10-15)

ExampleImplment the following function using a MUX F(A,B,C) = S (1,2,6,7)

Fig. 4.27

Implment the following function using a MUX F(A, B, C, D) = S(1, 3, 4, 11, 12, 13, 14, 15)

4-11 Multiplexer (12-15)

Three-State Gates A multiplexer can be constructed with three-state

gates. Output state: 0, 1, and high-impedance (open circuit) When the control input =1 :

• The output is enabled.• The gate behave like a conventional buffer, with the

output is equal to normal input. When the control input=0 :

• The output is disabled • The gate goes to a high-impedance state , regardless the

value of the normal input.

4-11 Multiplexer (13-15)

ExampleTwo -to-one-line multiplexer with three state gates

4-11 Multiplexer (14-15)

ExampleFour-to-one-line multiplexer using decoder with three state gates

4-11 Multiplexer (15-15)

ExampleFour-to-one-line multiplexer with three state gates The control inputs to the buffers determine which one

of the four normal inputs I0 to I3 will be connected to output line.

No more than one buffer may be in the active state at any given time.

The connected buffers must be controlled so that only 1 thee-state buffer has access to the output while all other buffers are maintained in a high-impedance state.

One way to ensure that no more than one control input is active at any given time is to use a decoder .

When E=0 high impedance state (all buffers are disable)

When E=1 one of the three buffers will be active.