CPSC 121: Models of Computation 2012 Summer Term 2

CPSC 121: Models of Computation2012 Summer Term 2

Building & Designing Sequential Circuits

Steve Wolfman, based on notes by Patrice Belleville and others

Outline

• Prereqs, Learning Goals, and Quiz Notes

• Problems and Discussion– A Pushbutton Light Switch– Memory and Events: D Latches & Flip-Flops– General Implementation of DFAs

(with a more complex DFA as an example)– How Powerful are DFAs?

• Next Lecture Notes

Learning Goals: Pre-Class

We are mostly departing from the readings to talk about a new kind of circuit on our way to a full computer: sequential circuits.

The pre-class goals are to be able to:– Trace the operation of a deterministic finite-

state automaton (represented as a diagram) on an input, including indicating whether the DFA accepts or rejects the input.

– Deduce the language accepted by a simple DFA after working through multiple example inputs.

Learning Goals: In-Class

By the end of this unit, you should be able to:– Translate a DFA to a corresponding sequential

circuit, but with a “hole” in it for the circuitry describing the DFA’s transitions.

– Describe the contents of that “hole” as a combinational circuitry problem (and therefore solve it, just like you do other combinational circuitry problems!).

– Explain how and why each part of the resulting circuit works.

Where We Are inThe Big Stories

Theory

How do we model computational systems?

Now: With our powerful modelling language (pred logic), we can prove things like universality of NOR gates for combinational circuits.

Our new model (DFAs) are sort of full computers.

Hardware

How do we build devices to compute?

Now: Learning to build a new kind of circuit with

memory that will be the key new feature we need to build full-blown computers!

(Something you’ve seen in lab from a new angle.)

Outline

• Prereqs, Learning Goals, and Quiz Notes

Problem: Push-Button Light Switch

Problem: Design a circuit to control a light so that the light changes state any time its “push-button” switch is pressed.

(Like the light switches in Dempster: Press and release, and the light changes state. Press and release again, and it changes again.)

A Light Switch “DFA”

light off

light on

pressed

This Deterministic Finite Automaton (DFA) isn’t really about accepting/rejecting; its current state is the state of the light.

Problem: Light Switch

Problem: Design a circuit to control a light so that the light changes state any time its “push-button” switch is pressed.

Identifying inputs/outputs: consider these possible inputs and outputs:

Input1: the button was pressedInput2: the button is downOutput1: the light is onOutput2: the light changed states

Which are most useful for this problem?

a.Input1 and Output1

b.Input1 and Output2

c.Input2 and Output1

d.Input2 and Output2

e.None of these9

COMPARE TO: Lecture 2’s Light Switch

Problem: Design a circuit to control a light so that the light changes state any time its switch is flipped.

Identifying inputs/outputs: consider these possible inputs and outputs:

Input1: the switch flippedInput2: the switch is onOutput1: the light is onOutput2: the light changed states

Which are most useful for this problem?

a.Input1 and Output1

b.Input1 and Output2

c.Input2 and Output1

d.Input2 and Output2

e.None of these10

Outline

• Prereqs, Learning Goals, and !Quiz Notes

Departures from Combinational Circuits

MEMORY:We need to “remember” the light’s state.

EVENTS:We need to act on a button push rather than in response to an input value.

Problem: How Do We Remember?

We want a circuit that:• Sometimes… remembers its current state.• Other times… loads a new state to remember.

13Sounds like a choice.

What circuit element do we have for modelling choices?

Worked Problem: “Muxy Memory”

How do we use a mux to store a bit of memory? We choose to remember on a control value of 0 and to load a new state on a 1.

1output

new data

control14

We use “0” and “1” because that’s how MUXes are usually labelled.

Worked Problem: Muxy Memory

How do we use a mux to store a bit of memory? We choose to remember on a control value of 0 and to load a new state on a 1.

1output (Q)

old output (Q’)

new data (D)

control (G)

This violates our basic combinational constraint: no cycles.15

Truth Table for “Muxy Memory”

Fill in the MM’s truth table:

G D Q'

a. b. c. d. e.Q

None of

Worked Problem: Truth Table for “Muxy Memory”

Worked Problem: Write a truth table for the MM: G D Q' Q

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 1

Like a “normal” mux table, but what happens when Q' Q?17

Worked Problem: Truth Table for “Muxy Memory”

Worked Problem: Write a truth table for the MM: G D Q' Q

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 1

Q' “takes on” Q’s value at the “next step”.18

“D Latch” Symbol + Semantics

We call a “muxy memory” a “D latch”.

When G is 0, the latch maintains its memory.

When G is 1, the latch loads a new value from D.

1output (Q)

old output (Q’)

new data (D)

control (G) 19

D Latch Symbol + Semantics

1output (Q)

old output (Q’)

new data (D)

control (G) 20

D Latch Symbol + Semantics

output (Q)

new data (D)

control (G)

Hold On!!

Why does the D Latch have two inputs and one output when the mux inside has THREE inputs and one output?

a. The D Latch is broken as is; it should have three inputs.

b. A circuit can always ignore one of its inputs.

c. One of the inputs is always true.

d. One of the inputs is always false.

e. None of these (but the D Latch is not broken as is).

Using the D Latch for Circuits with Memory

Problem: What goes in the cloud? What do we send into G?

GQ Combinational

Circuit to calculatenext state

We assume we just want Q as the output.

Using the D Latch for Our Light Switch

Problem: What do we send into G?

no (0 bit) input output

current light state

a. T if the button is down, F if it’s up.b. T if the button is up, F if it’s down.c. Neither of these. 24

A Timing Problem:We Need EVENTS!

output

“pulse” when

button is pressed

current light state

button pressed

As long as the button is down, D flows to Q flows through the NOT gate and back to D...

which is bad!25

A Timing Problem, Metaphor(from MIT 6.004, Fall 2002)

What’s wrong with this tollbooth?

P.S. Call this a “bar”, not a “gate”, or we’ll tie ourselves in (k)nots.

A Timing Solution, Metaphor(from MIT 6.004, Fall 2002)

Is this one OK?

A Timing Problem

output

“pulse” when

button is pressed

current light state

button pressed

As long as the button is down, D flows to Q flows through the NOT gate and back to D...

which is bad!28

A Timing Solution (Almost)

output

button pressed

Never raise both “bars” at the same time.

A Timing Solution

output

The two latches are never enabled at the same time (except for the moment needed for the NOT gate on the left to compute, which is so short that no “cars” get through).

A Timing Solution

output

button pressed

button press signal

Button/Clock is LO (unpressed)

output

We’re assuming the circuit has been set up and is “running normally”. Right now, the light is off (i.e., the output of the right latch is 0).

Button goes HI (is pressed)

output

This stuff is processing a new signal.

Propagating signal.. left NOT, right latch

output

Propagating signal.. right NOT (steady state)

output

Why doesn’t the left latch update?a.Its D input is 0.b.Its G input is 0.c.Its Q output is 1.d.It should update!

Button goes LO (released)

outputLO

Propagating signal..left NOT

output

Propagating signal..left latch (steady state)

output

And, we’re done with one cycle.How does this compare to our initial state?

Master/Slave D Flip-Flop Symbol + Semantics

When CLK goes from 0 (low) to 1 (high), the flip-flop loads a new value from D.

Otherwise, it maintains its current value.

output (Q)

new data (D)

control or

“clock” signal (CLK)

output (Q)

new data (D)

control or

output (Q)

new data (D)

control or

new data

clock signal

Q output

42We rearranged the clock and D inputs and the output to match Logisim.

Below we use a slightly different looking flip-flop.

Why Abstract?

Logisim (and real circuits) have lots of flip-flops that all behave very similarly:– D flip-flops, – T flip-flops, – J-K flip-flops, – and S-R flip-flops.

They have slightly different implementations… and one could imagine brilliant new designs that are radically different inside.

Abstraction allows us to build a good design at a high-level without worrying about the details.

43Plus… it means you only need to learn about D flip-flops’ guts.

The others are similar enough so we can just take the abstraction for granted.

Outline

How Do Computers Execute Programs?

• High-level languages (Java/Racket) are translated into low-level machine language

• A machine language program is a list of instructions in a representation scheme close to “plain” binary (e.g., 4 bits for the type of instruction, 4 bits for what part of the computer the result goes to, etc.)

• Each instruction has a (barely) human-readable version

• After it’s done with an instruction, the computer (usually) executes the next instruction in the list

Simplified Example(sum of 1..n)

(1) sum 0

(2) is n = 0?

(3) if the answer was yes, go to (7)

(4) sum sum + n

(5) n n - 1

(6) go to (2)

(7) halt

If the computer executed all instructions in order, there’d be no loops or recursion!

Fortunately, “branch” instructions (like (3)) tell the computer to go elsewhere.

Simplified Example, Complicated Execution

(1) sum 0

(2) is n = 0?

(3) if the answer was yes, go to (7)

(4) sum sum + n

(5) n n - 1

(6) go to (2)

(7) halt

To run faster, the computer starts executing one instruction even before it finishes the last.

But then what does it do with (3)?Does it execute (4) or (7)?

Branch Prediction Machine

To pre-execute a “branch”, the computer guesses which instruction comes next.

Here’s one reasonable guess: If the last branch was “taken” (like going to (7) from (3)), take the next. If it was “not taken” (like going to (4) from (3)), don’t take the next.

48Why? In recursion, how often do we hit

the base case vs. the recursive case?

Implementing the Branch Predictor (First Pass)

Here’s the corresponding DFA. (Instead of accept/reject, we care about the current state.)

yes no

nottaken

Experiments show it generally works well to add “inertia”so that it takes two “wrong guesses” to change the prediction…

taken the last branchwas taken

not taken the last branchwas not taken

yes we predict thenext branch will be taken

no we predict thenext branch will be not taken

Implementing the Branch Predictor (Final Version)

Here’s a version that takes two wrong guesses in a row to admit it’s wrong:

Can we build a branch prediction circuit?

nottaken

takentaken

not taken

Abstract Template for a DFA Circuit

compute next state

store current

Each time the clock “ticks” move from one state to the next.

Template for a DFA Circuit

Each time the clock “ticks” move from one state to the next.

Q Combinationalcircuit to calculatenext state/output

Each of these lines (except the clock) may carry multiple bits; the D flip-flop may be several flip-flops to store several bits.

How to Implement a DFA: Slightly Harder

(1) Number the states and figure out b: the number of bits needed to store the state number.

(2) Lay out b D flip-flops. Together, their memory is the state as a binary number.

(3) Build a combinational circuit that determines the next state given the input and the current state.

(4) Use the next state as the new state of the flip-flops.

How to Implement a DFA: Slightly Easier MUX Solution

(3) For each state, build a combinational circuit that determines the next state given the input.

(4) Send the next states into a MUX with the current state as the control signal: only the appropriate next state gets used!

(5) Use the MUX’s output as the new state of the flip-flops.

54With a separate circuit for each state, they’re often very simple!

Implementing the PredictorStep 1

nottaken

takentaken

not takenWhat is b (the number of 1-bit flip-flops

needed to represent the state)?a.0, no memory neededb.1c.2d.3e.None of these

As always, we use numbers to represent the inputs:

taken = 1not taken = 0

Just Truth Tables...

Current State input New state

0 0 0 0 0

0 0 1 0 1

nottaken

takentaken

not taken

What’s in this row?a.0 0b.0 1c.1 0d.1 1e.None of these.

Reminder: not taken = 0 taken = 1

Current State input New state

0 0 0 0 0

0 0 1 0 1

0 1 0 0 0

0 1 1 1 1

1 0 0 0 0

1 0 1 1 1

1 1 0 1 0

1 1 1 1 1

nottaken

takentaken

not taken

Reminder: not taken = 0 taken = 1

Implementing the Predictor:Step 3

We always use this pattern.

In this case, we need two flip-flops.

Q Combinationalcircuit to calculatenext state/output

Let’s switch to Logisim schematics...58

sright

Implementing the Predictor: Step 5 (easier than 4!)

The MUX “trick” here is much like in the ALU from lab!

sright

Implementing the Predictor: Step 4

srightIn state number 0, what should be the new value of sleft?Hint: look at the DFA, not at the circuit!a.inputb.~inputc.1d.0e.None of these.

In state number 1, what’s the new value of sleft?a.inputb.~inputc.1d.0e.None of these.

sright

sleft sright input sleft' sright'

0 0 0 0 0

0 0 1 0 1

0 1 0 0 0

0 1 1 1 1

1 0 0 0 0

1 0 1 1 1

1 1 0 1 0

1 1 1 1 1

sright

In state number 0, what’s the new value of sright?a.inputb.~inputc.1d.0e.None of these.

sright

TADA!! 69

sright

You can often simplify, but that’s not the point.

sright

Just for Fun: Renaming to Make a Pattern Clearer...

pred last input pred' last'

0 0 0 0 0

0 0 1 0 1

0 1 0 0 0

0 1 1 1 1

1 0 0 0 0

1 0 1 1 1

1 1 0 1 0

1 1 1 1 1

nottaken

takentaken

not taken

Outline

Steps to Build a Powerful Machine

(3) For each state, build a combinational circuit that determines the next state given the input.

(4) Send the next states into a MUX with the current state as the control signal: only the appropriate next state gets used!

(5) Use the MUX’s output as the new state of the flip-flops.

73With a separate circuit for each state, they’re often very simple!

How Powerful Is a DFA?

DFAs can model situations with a finite amount of memory, finite set of possible inputs, and particular pattern to update the memory given the inputs.

How does a DFA compare to a modern computer?

a.Modern computer is more powerful.

b.DFA is more powerful.

c.They’re the same.74

Where We’ll Go From Here...

We’ll come back to DFAs again later in lecture.

In lab you have been and will continue to explore what you can do once you have memory and events.

And, before long, how you combine these into a working computer!

Also in lab, you’ll work with a widely used representation equivalent to DFAs: regular expressions.

Outline

Learning Goals: In-Class

By the end of this unit, you should be able to:– Translate a DFA to a corresponding sequential

circuit, but with a “hole” in it for the circuitry describing the DFA’s transitions.

– Describe the contents of that “hole” as a combinational circuitry problem (and therefore solve it, just like you do other combinational circuitry problems!).

– Explain how and why each part of the resulting circuit works.

Next Lecture Learning Goals: Pre-Class

By the start of class, you should be able to:– Convert sequences to and from explicit formulas

that describe the sequence.– Convert sums to and from summation/”sigma”

notation.– Convert products to and from product/”pi”

notation.– Manipulate formulas in summation/product

notation by adjusting their bounds, merging or splitting summations/products, and factoring out values.

Next Lecture Prerequisites

See the Mathematical Induction Textbook Sections at the bottom of the “Readings and Equipment” page.

Complete the open-book, untimed quiz on Vista that’s due before the next class.

CPSC 121: Models of Computation 2012 Summer Term 2

Documents

Transcript of CPSC 121: Models of Computation 2012 Summer Term 2

Snick snack CPSC 121: Models of Computation 2008/9 Winter Term 2 Sets Steve Wolfman, based on notes by Patrice Belleville and others.

Snick snack CPSC 121: Models of Computation 2008/9 Winter Term 2 Propositional Logic: A First Model of Computation Steve Wolfman, based on notes by Patrice.

Snick snack CPSC 121: Models of Computation 2011 Winter Term 1 Propositional Logic, Continued Steve Wolfman, based on notes by Patrice Belleville and.

Snick snack CPSC 121: Models of Computation 2013W2 Introduction to Induction Steve Wolfman 1.

CPSC 121: Models of Computation 2012 Summer Term 2

Snick snack CPSC 121: Models of Computation 2011 Winter Term 1 Sets Steve Wolfman, based on notes by Patrice Belleville and others 1.

Snick snack CPSC 121: Models of Computation 2009 Winter Term 1 Proof (First Visit) Steve Wolfman, based on notes by Patrice Belleville, Meghan Allen.

CPSC 121: Models of Computation 2009 Winter Term 1

CPSC 121: Models of Computation 2008/9 Winter Term 2

Snick snack CPSC 121: Models of Computation 2010 Winter Term 2 DFAs in Depth Benjamin Israel bisrael@cs.ubc.ca Notes heavily borrowed from Steve Wolfman’s,

CPSC 121: Models of Computation Unit 7: Proof Techniques Based on slides by Patrice Belleville and Steve Wolfman.

CPSC 121: Models of Computation Unit 6 Rewriting Predicate Logic Statements Based on slides by Patrice Belleville and Steve Wolfman.

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CPSC 121: Models of Computation Unit 5 Predicate Logic Based on slides by Patrice Belleville and Steve Wolfman.

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CPSC 121: Models of Computation

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Snick snack CPSC 121: Models of Computation 2009 Winter Term 1 Introduction & Motivation Steve Wolfman, based on notes by Patrice Belleville and others.

CPSC 121: Models of Computation - University of British ...cs121/2016W2/slides/gao/0... · CPSC 121: Models of Computation Section 202 ... Jan 1st Feb 24th Jul 24th Jul 31st Sept

Snick snack CPSC 121: Models of Computation 2010/11 Winter Term 2 Propositional Logic: A First Model of Computation Steve Wolfman, based on notes by.