Counter Example 3-bit synchronous binary counter using D FF’s Step (1): State Diagram.

Counter Example

• 3-bit synchronous binary counter using D FF’s• Step (1): State Diagram

• Step (2): State Assignment– Use variables (A,B,C) and 3-bit binary assignment

• Step (3): State Transition Table

• Step (4): Derivation of Next State Equations

• Step (5): Logic Diagram

Sequence Detector

• Design sequence detector (for 1101) using J-K FF• Step (1): State Diagram

• Steps (2) and (3): State Assignment & State Transition Table

Transition J Input K Input

0 -> 0 0 x

0 -> 1 1 x

1 -> 0 x 1

1 -> 1 x 0

• Step (4): Derivation of Next State and Output Equations

• Step (5): Logic Diagram

Conversion to NAND-Gate Circuits

A + BC + D E'F

BCDE'F

Simplification Goals

• Goal -- minimize the cost of realizing a switching function

• Cost measures and other considerations– Number of gates

– Number of levels

– Gate fan in and/or fan out

– Interconnection complexity

– Preventing hazards

• Two-level realizations– Minimize the number of gates (terms in switching function)

– Minimize the fan in (literals in switching function)

Example

g(A,B,C) = AB + A B + AC

Determine the form and the number of terms and literals in each of the following.

Two-level form, three products , two sums, six literals.

f(X,Y,Z) = X Y(Z + Y X) + Y Z

Four-level form, four products, two sums, seven literals.

--------------------

Minimization Methods

• Commonly used techniques– Boolean algebra postulates and theorems

– Karnaugh maps

– Quine-McCluskey method

Minimum SOP and POS Representations

• The minimum sum of products (MSOP) of a function, f, is a SOP representation of f that contains the fewest number of product terms and fewest number of literals of any SOP representation of f.

• Example -- f(a,b,c,d) = m(3,7,11,12,13,14,15) = ab + acd + acd = ab + cd

• The minimum product of sums (MPOS) of a function, f, is a POS representation of f that contains the fewest number of sum terms and the fewest number of literals of any POS representation of f.

• Example -- f(a,b,c,d) = M(0,1,2,4,5,6,8,9,10) = (a + c)(a + d)(a + b + d)(b + c + d) = (a +c)(a + d)(b + c)(b + d)

Karnaugh Maps

• Karnaugh maps (K-maps) -- convenient tool for representing switching functions of up to six variables.

• K-maps form the basis of useful heuristics for finding MSOP and MPOS representations.

• An n-variable K-map has 2n cells with each cell corresponding to a row of an n-variable truth table.

• K-map cells are labeled with the corresponding truth-table row.

• K-map cells are arranged such that adjacent cells correspond to truth rows that differ in only one bit position (logical adjacency).

• Switching functions are mapped (or plotted) by placing the function’s value (0,1,d) in each cell of the map.

Figure Venn diagram and equivalent K-mapfor two variables

A B f(A B )

(a ) (b ) (c )

(e ) ( f)

A B A B A Bm

Figure Venn diagram and equivalent K-mapfor three variables

m 2 m 6

m 1 m 3 m 7 m 5

0 2 6 4

1 3 7 5

A B C A B CA B C

A B C m 0m 1

m 6m 7

0 2 6 4

1 3 7 5

0 0 0 1 1 1 1 0

(b ) (c )

(e ) ( f)

Plotting (Mapping) Functions in Canonical Form on a K-map

• Let f be a switching function of n variables where n 6.

• Assume that the cells of the K-map are numbered from 0 to 2n where the numbers correspond to the rows of the truth table of f.

• If mi is a minterm of f, then place a 1 in cell i of the K-map.

• Example -- f(A,B,C) = m(0,3,5)

• If Mi is a maxterm of f, then place a 0 in cell i.

• Example -- f(A,B,C) = M(1,2,4,6,7)

• If di is a don’t care of f, then place a d in cell i.

Figure Plotting functions on K-maps

0 0 0 1 1 1 1 00 2 6 4

1 3 7 5

0 1 0 1C

0 0 0 1 1 1 1 00 2 6 4

1 3 7 5

0 0 0 1 1 1 1 00 2 6 4

1 3 7 5

1 1 1C

(a ) (b )

(c ) (d )

f(A,B,C) = m(0,3,5) = M(1,2,4,6,7)

Figure K-maps for f(a,b,Q,G) (a) Minterm form. (b) Maxterm form.

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

1 1 1 1

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

(a ) (b )

f(a,b,Q,G) = m(0,3,5,7,10,11,12,13,14,15) = M(1,2,4,6,8,9)

Figure : f(Q,G,b,a).

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

1 1 1 1

f(Q,G,b,a) = m(0,12,6,14,9,13,3,7,11,15) = m(0,3,6,7,9,11,12,13,14,15)

(a) Venn diagram form. (b) Sum of minterms. (c) Maxterms.

0 0 0 1 1 1 1 00 2 6 4

1 3 7 5

0 0 0 1 1 1 1 00 2 6 4

1 3 7 5

(b ) (c )

U n iv e rsa l se t

f(A,B,C) = AB + BC

. (a) Maxterms, (b) Minterms, (c) Minterms of f .

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

A(A + C )

(B + C + D )

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

1 1 1 1

(a ) (b )

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

(B + C )

f(A,B,C,D) = (A + C)(B + C)(B + C + D)

.(a) K-map of f, (b) K-map of f.

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

(a ) (b )

f(A,B,C,D)= (A+B)(A+C+D)(B+C+D)

Simplification of Switching FunctionsUsing K-maps

• K-map cells that are physically adjacent are also logically adjacent. Also, cells on an edge of a K-map are logically adjacent to cells on the opposite edge of the map.

• If two logically adjacent cells both contain logical 1s, the two cells can be combined to eliminate the variable that has value 1 in one cell’s label and value 0 in the other.

• This is equivalent to the algebraic operation, aP + aP =P where P is a product term not containing a or a.

• Example -- f(A,B,C,D) = m(1,2,4,6,9)

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

S tep 2

S tep 1

S tep 3

f(A,B,C,D) = m(1,2,4,6,9)

Simplification Guidelines for K-maps

• Each cell of an n-variable K-map has n logically adjacent cells.

• Cells may be combined in groups of 2,4,8,…,2k.

• A group of cells can be combined only if all cells in the group have the same value for some set of variables.

• Always combine as many cells in a group as possible. This will result in the fewest number of literals in the term that represents the group.

• Make as few groupings as possible to cover all minterms. This will result in the fewest product terms.

• Always begin with the “loneliest” cells.

Figure 3.11 K-map illustrating implicants

0 0 0 1 1 1 1 00 2 6 4

Minterms: {AB C, A BC, A BC, ABC, ABC}

Groups of two minterms: {A B, AB, A C, BC, BC}

Groups of four minterms: {B}

MSOP = A C + B

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

(a ) (b )

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

(c) (d )

f(A,B,C,D) = m(2,3,4,5,7,8,10,13,15)

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

(a ) (b )

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

f(A,B,C,D) = m(2,3,4,5,7,8,10,13,15)

Use a K-MAP to simplify the following function

, , , 1,7,8,12 3,6,9,10F a b c d m d

Four-variable K-Mapab

cd 00 01 11 10

, , , 1,7,8,12 3,6,9,10F a b c d m d

Four-variable K-Mapab

cd 00 01 11 10

, , ,F a b c d abd acd acd

f(A,B,C,D) = m(0,5,7,8,10,12,14,15)

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

(a ) (b )

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

(c) (d )

f(A,B,C,D) = m(1,2,3,6) = AC + BC

0 0 0 1 1 1 1 00 2 6 4

f(A,B,C,D) = BD + BC + BCD

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 1 1

2 6 1 4 1 0

C D 0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

C DA B

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

(a ) (b )

A B0 0 0 1 1 1 1 0

0 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

f(A,B,C,D) = m(0,4,5,7,8,10,14,15)

Find the minimum POS form of the functionf(A,B,C,D) = M(0,1,2,3,6,9,14)

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

(a ) (b )

Algorithm -- Finding MPOS of f from f

1. Plot the complement function f on the K-map.

2. Produce a MSOP of f.

3. Complement f and use DeMorgan’s theorem to produce a MSOP of f.

Find the MPOS of the following function f(A,B,C,D) = M(0,1,2,3,6,9,14)

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

(a ) (b )

K-map of f

f = A B + B C D + BCD

f = (A + B)(B + C + D )(B + C + D)

Example 3.19 -- Minimum covers off(A,B,C,D) = M (3,4,6,8,9,11,12,14) and its complement.

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

Figure 3.21

Figure Deriving POS and SOP forms of a function.

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

Example -- Minimizing a Function with Don’t Cares.f(A,B,C,D) = m(1,3,4,7,11) + d(5,12,13,14,15)

= M(0,2,6,8,9,10) D(5,12,13,14,15)

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

SOP POS

Example Design a circuit to distinguish BCD digits 5 from those 5.

A B C D

L o g icc ircu it f

M in te rm f(A , B , C , D )

0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

0123456789

1 01 11 21 31 41 5

0000011111dddddd

Figure block diagram and truth table.

Example

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 11

2 6 1 4 1 0

Figure 3.26 Use of don’t cares for SOP and POS forms.

MSOP MPOS

f(A,B,C,D) = A + BD + BC; f(A,B,C,D) = (A + B)(A + C + D)

WHAT IS A DECODER• In older days, the (good) printers used to be like typewriters:

– To print “A”, a wheel turned, brought the “A” key up, which then was struck on the paper.

• Letters are encoded as 8 bit codes inside the computer.– When the particular combination of bits that encodes “A” is

detected, we want to activate the output line corresponding to A– (Not actually how the wheels worked)

• How to do this “detection” : decoder

• General idea: given a k bit input, – Detect which of the 2^k combinations is represented– Produce 2^k outputs, only one of which is “1”.

Decoders and M

ultiplexers

WHAT A DECODER DOES• A n-to-2n decoder takes an n-bit input and produces 2n outputs. The n inputs

represent a binary number that determines which of the 2n outputs is uniquely true.

• A 2-to-4 decoder operates according to the following truth table.– The 2-bit input is called S1S0, and the four outputs are Q0-Q3.– If the input is the binary number i, then output Qi is uniquely true.

• For instance, if the input S1 S0 = 10 (decimal 2), then output Q2 is true, and Q0, Q1, Q3 are all false.

• This circuit “decodes” a binary number into a “one-of-four” code.

S1 S0 Q0 Q1 Q2 Q3 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1

Decoders and M

ultiplexers

ENABLE INPUTS• Many devices have an additional enable input, which is used to “activate” or

“deactivate” the device.

• For a decoder,

– EN=1 activates the decoder, so it behaves as specified earlier. Exactly one of the outputs will be 1.

– EN=0 “deactivates” the decoder. By convention, that means all of the decoder’s outputs are 0.

• We can include this additional input in the decoder’s truth table:

EN S1 S0 Q0 Q1 Q2 Q3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1

Decoders and M

ultiplexers

BLOCKS AND ABSTRACTION

• Decoders are common enough that we want to encapsulate them and treat them as an individual entity.

• Block diagrams for 2-to-4 decoders are shown here. The names of the inputs and outputs, not their order, is what matters.

• A decoder block provides abstraction:– You can use the decoder as long as you know its truth table or equations,

without knowing exactly what’s inside.– It makes diagrams simpler by hiding the internal circuitry.– It simplifies hardware reuse. You don’t have to keep rebuilding the

decoder from scratch every time you need it.• These blocks are like functions in programming!

Q0 = S1’ S0’Q1 = S1’ S0Q2 = S1 S0’Q3 = S1 S0

Decoders and M

ultiplexers

A 3-TO-8 DECODER• Larger decoders are similar. Here is a 3-to-8 decoder.

– The block symbol is on the right.

– A truth table (without EN) is below.

– Output equations are at the bottom right.

• Again, only one output is true for any input combination.

S2 S1 S0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1

Q0 = S2’ S1’ S0’Q1 = S2’ S1’ S0Q2 = S2’ S1 S0’Q3 = S2’ S1 S0Q4 = S2 S1’ S0’Q5 = S2 S1’ S0Q6 = S2 S1 S0’Q7 = S2 S1 S0

Decoders and M

ultiplexers

SUMMARY• A n-to-2n decoder generates the minterms of an n-variable function.

– As such, decoders can be used to implement arbitrary functions.

– Later on we’ll see other uses for decoders too.

• Some variations of the basic decoder include:– Adding an enable input.

– Using active-low inputs and outputs to generate maxterms.

• We also talked about:– Applying our circuit analysis and design techniques to understand

and work with decoders.

– Using block symbols to encapsulate common circuits like decoders.

– Building larger decoders from smaller ones.

Decoders and M

ultiplexers

MULTIPLEXERS• A 2n-to-1 multiplexer sends one of 2n input lines to a single

output line. – A multiplexer has two sets of inputs:

• 2n data input lines

• n select lines, to pick one of the 2n data inputs

– The mux output is a single bit, which is one of the 2n data inputs.

• The simplest example is a 2-to-1 mux:

• The select bit S controls which of the data bits D0-D1 is chosen:– If S=0, then D0 is the output (Q=D0).

– If S=1, then D1 is the output (Q=D1).

Q = S’ D0 + S D1

Decoders and M

ultiplexers

MORE TRUTH TABLE ABBREVIATIONS

• Here is a full truth table for this 2-to-1 mux, based on the equation:

• Here is another kind of abbreviated truth table.– Input variables appear in the output column.– This table implies that when S=0, the output Q=D0, and when

S=1 the output Q=D1.– This is a pretty close match to the equation.

S D1 D0 Q 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1

Q = S’ D0 + S D1

S Q 0 D0 1 D1

Decoders and M

ultiplexers

A 4-TO-1 MULTIPLEXER• Here is a block diagram and abbreviated truth table for a 4-

to-1 mux.

• Be careful! In LogicWorks the multiplexer has an active-low EN input signal. When EN’ = 1, the mux always outputs 1. EN’ S1 S0 Q

0 0 0 D0 0 0 1 D1 0 1 0 D2 0 1 1 D3 1 x x 1

Q = S1’ S0’ D0 + S1’ S0 D1 + S1 S0’ D2 + S1 S0 D3

Decoders and M

ultiplexers

IMPLEMENTING FUNCTIONS WITH MULTIPLEXERS

• Muxes can be used to implement arbitrary functions.

• One way to implement a function of n variables is to use an n-to-1 mux:

– For each minterm mi of the function, connect 1 to mux data input Di. Each data input corresponds to one row of the truth table.

– Connect the function’s input variables to the mux select inputs. These are used to indicate a particular input combination.

• For example, let’s look at f(x,y,z) = m(1,2,6,7).

x y z f 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1

Decoders and M

ultiplexers

A MORE EFFICIENT WAY

• We can actually implement f(x,y,z) = m(1,2,6,7) with just a 4-to-1 mux, instead of an 8-to-1.

• Step 1: Find the truth table for the function, and group the rows into pairs. Within each pair of rows, x and y are the same, so f is a function of z only.

– When xy=00, f=z– When xy=01, f=z’– When xy=10, f=0– When xy=11, f=1

• Step 2: Connect the first two input variables of the truth table (here, x and y) to the select bits S1 S0 of the 4-to-1 mux.

• Step 3: Connect the equations above for f(z) to the data inputs D0-D3.

x y z f 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1

June 18th, 2008D

ecoders and Multiplexers

SUMMARY• A 2n-to-1 multiplexer routes one of 2n input lines to a single output line.• Just like decoders,

– Muxes are common enough to be supplied as stand-alone devices for use in modular designs.

– Muxes can implement arbitrary functions.

• We saw some variations of the standard multiplexer:– Smaller muxes can be combined to produce larger ones.– We can add active-low or active-high enable inputs.

• As always, we use truth tables and Boolean algebra to analyze things.

• On Monday, we will start discussing how to build circuits to do arithmetic.

June 18th, 2008D

ecoders and Multiplexers

SIGNED MAGNITUDE REPRESENTATION

• Humans use a signed-magnitude system: we add + or - in front of a magnitude to indicate the sign.

• We could do this in binary as well, by adding an extra sign bit to the front of our numbers. By convention:– A 0 sign bit represents a positive number.– A 1 sign bit represents a negative number.

• Examples:

11012 = 1310 (a 4-bit unsigned number)

0 1101 = +1310 (a positive number in 5-bit signed magnitude)

1 1101 = -1310 (a negative number in 5-bit signed magnitude)

0 0100 = +410 (a positive number in 5-bit signed magnitude)

1 0100 = -410 (a negative number in 5-bit signed magnitude)

June 24th, 2004Subtraction

ONE’S COMPLEMENT REPRESENTATION

• A different approach, one’s complement, negates numbers by complementing each bit of the number.

• We keep the sign bits: 0 for positive numbers, and 1 for negative. The sign bit is complemented along with the rest of the bits.

• Examples:

0 1101 = +1310 (a positive number in 5-bit one’s complement)

1 0010 = -1310 (a negative number in 5-bit one’s complement)

0 0100 = +410 (a positive number in 5-bit one’s complement)

1 1011 = -410 (a negative number in 5-bit one’s complement)

TWO’S COMPLEMENT

• Our final idea is two’s complement. To negate a number, complement each bit (just as for ones’ complement) and then add 1.

• Examples:11012 = 1310 (a 4-bit unsigned number)

0 1101 = +1310 (a positive number in 5-bit two’s complement)

1 0010 = -1310 (a negative number in 5-bit ones’ complement)

1 0011 = -1310 (a negative number in 5-bit two’s complement)

0 0100 = +410 (a positive number in 5-bit two’s complement)

1 1011 = -410 (a negative number in 5-bit ones’ complement)

1 1100 = -410 (a negative number in 5-bit two’s complement)

MORE ABOUT TWO’S COMPLEMENT

• Two other equivalent ways to negate two’s complement numbers:– You can subtract an n-bit two’s complement number from 2n.

– You can complement all of the bits to the left of the rightmost 1.

01101= +1310 (a positive number in two’s complement)10011= -1310 (a negative number in two’s complement)

00100= +410 (a positive number in two’s complement)11100= -410 (a negative number in two’s complement)

• Often, people talk about “taking the two’s complement” of a number. This is a confusing phrase, but it usually means to negate some number that’s already in two’s complement format.

1 0 0 0 0 0- 0 1 1 0 1 (+1310)

1 0 0 1 1 (-1310)

1 0 0 0 0 0- 0 0 1 0 0 (+410)

1 1 1 0 0 (-410)

TWO’S COMPLEMENT ADDITION

• Negating a two’s complement number takes a bit of work, but addition is much easier than with the other two systems.

• To find A + B, you just have to:– Do unsigned addition on A and B, including their sign bits. – Ignore any carry out.

• For example, to find 0111 + 1100, or (+7) + (-4): – First add 0111 + 1100 as unsigned numbers:

– Discard the carry out (1).– The answer is 0011 (+3).

0 1 1 1+ 1 1 0 0

1 0 0 1 1

Counter Example 3-bit synchronous binary counter using D FF’s Step (1): State Diagram.

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Channabasaveshwara Institute of Technologyvtu.babivenu.in/wp-content/uploads/2019/08/ANALOG... · Parity Generator/Checker 10. Synchronous Counter 11. Asynchronous Counter Average

PLACE LABEL HEREConsider this 2-bit ripple down counter. (a) ... State one difference between the design of a ripple counter and that of a synchronous counter. (1 mark) ... State one

Synchronous 4-Bit Up/Down Binary Counters With Dual Clock ... sheets/Counter- synchronous 4 bit... · Parallel Asynchronous Load for Modulo-N Count Lengths Asynchronous Clear ...

HEF4029B MSI Synchronous up/down counter, binary/decade counter

6 Synchronous State Machine Design...6 – Synchronous State Machine Design 2 Hardik A. Doshi, CE Department | 2131004 – Digital Electronics Design a counter to generate the repetitive

Synchronous Counter - Dronacharyaggn.dronacharya.info/CSE2Dept/Downloads/QuestionBank/odd/III sem... · Synchronous (Parallel) Counters Example: 2-bit synchronous binary counter (using

74HC193; 74HCT193 Presettable synchronous 4-bit binary … · 2015. 6. 16. · 1. General description The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate

74HC191 Presettable synchronous 4-bit binary up/down counter · PDF fileThis feature simplifies the design of multistage ... Presettable synchronous 4-bit binary up/down counter 7.

Synchronous Counters, ripple counter & other counters ...