Sequential Logic

(Materials taken from: Principles of Computer Hardware by Alan Clements )

Sequential vs. Combinational Circuits

• Combinatorial circuits: their outputs are computed entirely from their present inputs

• Sequential circuits: their outputs are computed using both the present input and their previous output– The idea of a next state

– A clock input triggers the transition from the current state to next state.

The Big Picture

Sequential Logic Elements

• Sequential logic can perform as many different functions as combinational logic

• Certain functions have been given names.

– Latch: a 1-bit memory element

– Register : m latches in a row and is able to store an m-bit word

– Shift register: special-purpose register that moves the bits of the word left or right

– Counter: special-purpose register that when triggered (i.e. clocked) increases its contents by 1

– State machines: moves from one state to another each time it is triggered

The Flip-Flop

• Basic building block of sequential circuits

Analysis by Assuming Initial Conditions

Truth Table

RS Flip-Flop

NAND Gate Implementation

Clocked RS Flip-Flop

NOR gate implementation NAND gate implementation

D Flip-Flop

D = 1 sets the RS flip-flop and D = 0 clears it

D Flip-Flop Chip

2 active low inputs called preset and clear- Unconditional - Set high in normal usage- Used on power-up

Registers

Registers transmit and receive data from busesFlip-flops are clocked to latch the data

RegistersThe most common sequential building block is the register. A register is N bits wide and has a load line for loading in a new value into the register.

Note that DFF simply loads old value when LD = 0. DFF i l d d l k l

V 0.4 57Copyright 2005. Thomson/Delmar Learning, All rights reserved.

is loaded every clock cycle.

Ways of Clocking a Flip-Flop

• A clocked flip-flop captures a digital value and holds it; three ways of clocking:1. Whenever the clock is asserted (i.e. a level-

triggered flip-flop).

2. Whenever the clock is changing state (i.e. an edge-triggered flip-flop).

3. Capture data on one edge of the clock and transfer it to output on the following edge (i.e. a master–slave flip-flop)

Level-Triggered FF

• The type of FF we have discussed so far

• Not appropriate for all applications

Edge-Triggered FF

• An edge-triggered flip-flop is clocked not by the level of the clock (i.e. high or low), but by the transition of the clock signal from zero to one, or one to zero. – Positive or rising-edge sensitive

– Negative or falling-edge sensitive

– The rising or falling edge of a pulse can have durations less than 1 ns

– Like an level-sensitive clock triggered by a infinitesimally short pulse

Edge-Triggered FF

Positive edge-triggered D flip-flop

Edge-Triggered FF

• Variation in the arrival time of clock pulses to FF clock inputs is called clock skew

• Caused by differences in the paths by which clock pulses reach flip-flops– Distance

– Temperature

– Age

Master-Slave FF

Timing Diagrams

JK Flip-Flop

Edge-triggered flip-flops

When a JK flip-flop is clocked, it behaves like an RS flip-flop (where J = S, K = R) for all input conditions except J = K = 1

Summary

• Flip-flops have internal state as well as external inputs---they are memory elements

• The most common forms of flip-flop are: D flip-flop, RS flip-flop, and JK flip-flop

• Flip-flops have two outputs: Q and Q

• Most flip-flops are clocked and the clock is used to trigger the flip-flop.

• Flip-flops often have unconditional preset and clear inputs used the set or clear the output

Shift Register• Shift register: bits can be moved one place right every

time the register is clocked

• Example, the binary pattern 01110101

becomes 00111010 after the shift register is clocked once

and 00011101 after it is clocked twice

and 00001110 after it is clocked three times, and so on

• After the first shift a 0 has been shifted in from the left-hand end and the 1 at the right-hand end has been lost

• Shifting 1 place right has the effect of dividing the number by 2; 1 place left corresponds to multiplying by 2

Right-Shift Register Using D FFs

Shift RegisterVery useful sequential building block Used to perform eitherVery useful sequential building block. Used to perform either parallel to serial data conversion or serial to parallel data conversion.

Copyright 2005. Thomson/Delmar Learning, All rights d

V 0.4 59

reserved.

Binary Counter Using JK Flip-Flops

CounterVery useful sequential building block. Used to generate memory y q g g yaddresses, or keep track of the number of times a datapath operation is performed.

Copyright 2005. Thomson/Delmar Learning, All rights d

V 0.4 58

reserved.