Collaboration enhances optical chip designprocess26 September 2016

Credit: Lawrence Berkeley National Laboratory

A unique collaboration between a U.S.telecommunications equipment provider and aDepartment of Energy (DOE) Office of Sciencenational laboratory has helped dramaticallyimprove design cycle times for future high-speedoptical networking components.

Computer scientists and mathematicians fromLawrence Berkeley National Laboratory's(Berkeley Lab) Computing Sciences organizationworked with engineers at Ciena, a leadingnetworking company, to speed up the process bywhich Ciena validates the design of its ASIC(application-specific integrated circuit) chips. Thecollaboration grew out of the existing relationshipbetween Ciena, a pioneer in high-bandwidthoptical transport technology, and the DOE'sEnergy Sciences Network (ESnet), which usesCiena products to support its high-speed network.

"Modern science requires fast global networks likeESnet, and almost all DOE network traffic happensto run over optical gear from Ciena," said InderMonga, director of ESnet. "ESnet doesn't transportquite as much traffic as, say, Google, but we havethe unique challenge of coping with massive singledata streams from detectors and instruments likethe Large Hadron Collider, the world's largest andmost powerful particle accelerator. This means weneed to exploit leading-edge networkingcomponents, and we're often early adopters ofthose components."

To help Ciena better utilize computational methodsin designing and producing their next-generationoptical networking products, John Shalf and JamesSethian of Berkeley Lab's Computational ResearchDivision (CRD) demonstrated the feasibility ofaccelerating computational verification of ForwardError Correction (FEC) codes, which are commonlyused in optical transmission equipment forcontrolling errors in data transmission.

Simulating 9 Quadrillion Bits of Data

To do this they modified a random numbergenerator library called MRG8 (multiple recursivegenerator with 8th-order recursion), which wasdeveloped by Kenichi Miura, a Berkeley Labaffiliate. Ciena's ASIC designers, led by KimRoberts, then used 8 million supercomputing hoursat Berkeley Lab's National Energy ResearchScientific Computing Center (NERSC)—provided byNERSC Director Sudip Dosanjh through theDirector's Discretionary Reserve—to test andvalidate the efficacy of the enhanced FEC codes inthe Ciena modems. The parameter study made useof a Task Farmer developed by NERSC's ShaneCanon to support high-throughput parameterresearch such as the Ciena FEC code study.

To show the benefits of this technology, the teamsimulated sending 9 quadrillion bits of data in anoisy environment, where the channel impairments

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caused about 500 trillion of these bits to be receivedin error, explained Masoud Ebrahimi, an engineerat Ciena.

"Our FEC mechanism corrected all the 500 trillionerrors and ensured us that the bit error rate isbelow 10-16," Ebrahimi said.

"Without custom ASICs to perform the calculationsrequired for high-speed FEC processing, modernhigh-speed networking would just not be possible,"Roberts said. "FEC is a way of adding extrainformation to an information signal, so that in caseanything is lost or corrupted during transmission,the original data stream can be recovered, up to apoint."

The process of validating FEC algorithms requiresrunning a set of sample experiments millions oftimes, to track when and where any transmissionerrors occur, explained Sethian, who leadsBerkeley Lab's Mathematics Group and the Centerfor Advanced Mathematics for Energy ResearchApplications. To improve this process and the FECcode itself, the Berkeley Lab team had to figure outhow to seed the experiments to ensure that theywere truly random and not secretly correlated orduplicated.

Using the parallel processing resources at NERSChad a dramatic impact on the time it took to run theexperiments and validate the design of the FECalgorithm. With NERSC resources, Ciena was ableto dramatically expand the scope of their study on acompressed timescale.

"We thought we could take advantage of massivelyparallel processing to run these things in parallelrather than sequentially," Sethian said. "And in theprocess we found that there turns out to be moreefficient and optimal ways to call these randomseeds and random generators to take advantage ofthese architectures."

Truly Random Numbers

To scale up on the parallel machine—in this case,NERSC's Edison system—required ensuring that therandom numbers were truly random and that eachof the processors was sampling a completely

different space in terms of the random numbergenerator, Shalf added.

"A conventional random number generator followsa predictable "pseudo-random" sequence thatrepeats itself eventually," he explained. "If you'renot careful, you can find yourself repeating thesame sequence and not explore as large of aspace as you had originally expected. Dr. Miura'sMRG8 generates a much longer pseudo-randomnumber sequence before it repeats itself, and alsoenables each of the parallel processors to beassigned its own starting point in the sequence thatis guaranteed to not overlap. MRG8 providesstronger guarantees that a larger space of FECcodes can be explored using parallel computation."

Ciena has now completed the various runs,evaluated the results, and now planning on next-steps. Monga sees this project as the beginning ofan ongoing collaboration that could yield additionaldesign and process improvements.

"If the entire industry is pushed forward just a littlebit by this collaboration, the market will moveforward, new technologies will evolve. That's goodfor DOE science," Monga said. "We look forward tothis partnership continuing to benefit the networkingcommunity."

Provided by Lawrence Berkeley NationalLaboratory

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APA citation: Collaboration enhances optical chip design process (2016, September 26) retrieved 2October 2021 from https://phys.org/news/2016-09-collaboration-optical-chip.html

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