Jose Schutt-Aine, UIUC-ECE(Jose is a fellow of IEEE. He served co-Editor in Chief of the IEEE-TCPMT

2007 – 2018.)http://emlab.Illinois.edu/jose

Co-Chair: Chris Bailey, U of Greenwich

Co-Design

Application Drivers• Data Centers• IoT• Automotive• HealthTechnology Drivers• High-Speed Links• SERDES• Silicon Photonics• 3D IC, TSV• 2.5D Packaging, Interposers

Motivations for Co-Design

Increased Product Quality

Decreased Product Cost

Decreased NRE Schedule, Effort

- Transistors- Nonlinear- SPICE- Scaling with tech

- Interconnects- Linear- EM Tools- Scaling with λ

- Transmission lines, sensors- Linear+Nonlinear- EM Extraction, SPICE, IBIS,…- Scaling with λ

Motivations for Co-Design

• What is the state of the art in co-design?• What system products will drive creation of new co-design

tools/methods?• What are the key challenges that need to be overcome?• What added value will new co-design tools/methods bring to

those products?• What needs to happen for these challenges to be overcome?• When will answers to the above become apparent?

Key Roadmapping Questions

Interconnect Evolution

VERTICAL• Bridge IC, Package, Board• Bridge System, Architecture, Layout• Bridge Synthesis, Analysis, Verification• Bridge Hardware, Software, FirmwareHORIZONTAL• Energy aware• Signal/power integrity aware• Stress/thermal aware• Security aware• Testing aware

Co-Design

Example: Unified Planning Tool (Die-Pkg-Pcb)

Early Planning Is Key!

• Unified workflow, including partitioning, floorplanning, • Capability to create abstract package models• Ability to visualize and modify component placement scenarios • Provision of dynamic manipulation of pin arrays within the abstract models• Preserving signal assignments and rules• Support for multiple package variables and PCB form factors • Standardization of interface data of system blocks• Enabling the interaction of design tools from different EDA vendors• Routability estimation and optimal routing algorithms• Ability to quickly provide accurate models• Multi-physics aware pathfinding environment• Design-for-Test and testability constraints for 3D integration

Pathfinding Methodologies

Routability Estimation and Routing

Flow of Chip-Package Co-Design

• OS and architecture co-design • Security and architecture co-design• Interconnect and architecture co-design• Device and architecture co-design • Technology and architecture co-design• Provide communication mechanisms between different design

layers.• Support growing functionalities and heterogeneity

requirements• Support thermal, power integrity, reliability management

Co-Design for Architecture

Co Design for Integrated Photonics

semiconductor and photonics worlds are merging, and the chip industry will start driving silicon photonics.

- Infrastructure from electronic design can be used- Connection of photonic components harder- Different time scales for heating and cooling- Photonic circuits are very sensitive to thermal changes- Account for electrical-optical-thermal interactions- Case for co-design tools is very strong

• Cross-Layer Design (Material, Device, Circuits, Systems)• Multiple Domain Co-Design (Analog, Digital, Mixed-Signal)• Packaging

• Quantum hardware:• Control electronics• System design and integration (SW-HW co-design)

Future Heterogeneous SystemsNeuromorphic Computers

Quantum Computing

Showstoppers• Multiphysics• Differences in scales and resolutions• Different design rules• Tools are old and slowPotential Solutions• Behavioral, Macro Modeling (e.g., IBIS-AMI, X- parameters)• Statistical modeling• Hardware, FPGAs• Artificial intelligence, machine learning• New algorithms• Quantum computing?

Challenges

• Jose Schutt-Aine, UIUC (Chair)

• Christopher Bailey, U of Greenwich, (co-Chair)

• Pavle Milosevic, Intel

• Aida Todri-Sanial, CNRS-LIRMM

• Carmen G. Almudever, Delft U of Tech

• Cheng Zhuo, Zhejiang University

• Ajay Joshi, Boston University

• Milos Popovic, Boston University

Thank You TWG Members• Ambrish Varma, Cadence

• Narayanan T Varadharajan, Cadence

• Herb Reiter, EDA2ASIC

• Richard Rao, Microchip

• Brandon Wang, Synopsys

• Youngsoo Lee, Synopsys

• Muhannad S. Bakir, Georgia Tech

• Vaishnav Srinivas, Qualcomm

• Kambiz Samadi, Qualcomm