Post on 16-Mar-2022
2010 IEDM SHORT COURSE15nm CMOS Technology
CMOS Technologies – Trends, Scaling and Issues
1IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
Scaling and Issues
Instructor: Thomas Skotnicki, STMicroelectronics, Fellow and Director of Advanced DevicesCrolles, France
Introduction
CMOS Technology Roadmap (ITRS) overview Density scaling (Gate length/pitch)Power scaling (low power/leakage) Voltage scaling
SOC requirements and prerogatives
OUTLINE
2IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
SOC requirements and prerogatives
Performance scaling – New insightBULKIII-V CHANNELSFINFETFDSOI
Variability for logic/for SRAM
Perspective
More Moore and More than Moore convergence for More Moore and More than Moore convergence for MultiMedia applicationsMultiMedia applicationsMore Moore and More than Moore convergence for More Moore and More than Moore convergence for MultiMedia applicationsMultiMedia applications
3IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
Mobile Internet DevicesHigh-Speed >2GHzLow Operation VddLow Stdby Leakage
Digital imaging
Technology trend Technology trend -- view view by ITRSby ITRSTechnology trend Technology trend -- view view by ITRSby ITRS
4IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
Introduction
CMOS Technology Roadmap (ITRS) overview Density scaling (Gate length/pitch)Power scaling (low power/leakage) Voltage scaling
SOC requirements and prerogatives
OUTLINE
5IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
SOC requirements and prerogatives
Performance scaling – New insightBULKIII-V CHANNELSFINFETFDSOI
Variability for logic/for SRAM
Perspective
ITRS 2009 : CALCULATED WITH MASTAR, IMPORTANT CHANGES INTRODUCED IN METHODOLOGY
6IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
20
1
1.5
2
2.5
3
3.5
4
SC
AL
ING
AS
OF
ITR
S 2
005
HP Tox_el, nm
LOP Tox_el, nm
LSTP Tox_el, nm
HP Vdd, mV
LOP Vdd, mV
LSTP Vdd, mV
HP Lg, nm
Vdd, mV
Tox, nm
Lg, nm
Even less Vddscaling than
Lg LOP readsat around 40nmrather than 20nm!
Reality has turned out to be more difficult than ITRS predictions
7IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
20.5
2005 2006 2007 2008 2009 2010
YEAR
LOP Lg, nm
LSTP Lg, nm
E v o lu tio n o f V D D (L S T P )
0
0 , 5
1
1 , 5
2
2 , 5
3
3 , 5
4
4 , 5
5
1 9 8 0 1 9 9 2 1 9 9 5 1 9 9 8 2 0 0 0 2 0 0 2 2 0 0 4 2 0 0 7 2 0 1 0 2 0 1 5
Y e a r o f p r o d u c ti o n (I T R S )
Vo
lt
5 V p la te a u
1 .2 V p la te a u
1 2 0 9 0 6 5 3 22 5 03 5 07 0 0 4 5
1 .1 V
5 0 0 1 8 0
R e g u la r D e c r e a se in 1 0 y e a r s
F r o m 5 V to 1 .2 V (x 0 .7 p e r n o d e )
1 .0 V
E v o lu tio n o f V D D (L S T P )
0
0 , 5
1
1 , 5
2
2 , 5
3
3 , 5
4
4 , 5
5
1 9 8 0 1 9 9 2 1 9 9 5 1 9 9 8 2 0 0 0 2 0 0 2 2 0 0 4 2 0 0 7 2 0 1 0 2 0 1 5
Y e a r o f p r o d u c ti o n (I T R S )
Vo
lt
5 V p la te a u
1 .2 V p la te a u
1 2 0 9 0 6 5 3 22 5 03 5 07 0 0 4 5
1 .1 V
5 0 0 1 8 0
R e g u la r D e c r e a se in 1 0 y e a r s
F r o m 5 V to 1 .2 V (x 0 .7 p e r n o d e )
1 .0 V
scaling than predicted !
HK Introduction,but before and after this point stagnation in scaling
STATIC POWER CRISIS ADDS TO DYNAMIC POWER CRISIS
8IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
POWER LIMITATION CHANGES PARADIGM
multicore
9IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
2500
3000
3500
Pe
rfo
rma
nce
In
de
x
SPEED-HUNGRY PARADIGM
DOES THE MOORE’s LAW CONTINUE ?
YES, since we sell to customers system performance rather than frequency
Pdyn = n x Frequency x Cload x Vdd2
10IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
0
500
1000
1500
2000
2500
0 1000 2000 3000 4000
Frequency (MHz)
Pe
rfo
rma
nce
In
de
x
1 core
2 cores
+POWER-THRIFTY
PARADIGM
=HUMAN NATURE
(CV/I)-1
SO….ONCE AGAIN WE NEED FREQUENCY, BUT BULK CANNOT OFFER IT ANY LONGER
ITRS 2009
11IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
RO FO=1
RO FO=4
Bulk
BulkFLAT
DIFFICULT CHALLENGES
12IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
ITRS 2009 HP Year 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024Lgate HP nm 29 27 24 22 20 18 17 15.3 14.0 12.8 11.7 10.7 9.7 8.9 8.1 7.4
Vdd V 1.00 0.97 0.93 0.90 0.87 0.84 0.81 0.78 0.76 0.73 0.71 0.68 0.66 0.64 0.62 0.60
EOT, Bulk nm 1 0.95 0.88 0.75 0.65 0.55 0.53…….. SOI '' 0.7 0.68 0.60 0.57 0.57 0.54 0.5…….. DG '' 0.77 0.7 0.67 0.64 0.62 0.59 0.57 0.55 0.53 0.5
ITRS 2009 LOP Year 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024
ITRS 2009 : MAIN FEATURES (1)
13IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
LOP Year 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024Lgate LOP nm 32 29 27 24 22 18 17 15.3 14.0 12.8 11.7 10.7 9.7 8.9 8.1 7.4
Vdd V 0.95 0.95 0.85 0.85 0.8 0.8 0.75 0.75 0.7 0.7 0.65 0.65 0.6 0.6 0.6 0.6EOT, Bulk nm 1 0.9 0.9 0.85 0.8…….. SOI 0.9 0.85 0.8 0.75 0.7 0.65…….. DG 0.8 0.8 0.75 0.73 0.7 0.7 0.65 0.65 0.6 0.6
ITRS 2009 LSTP Year 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024Lgate LSTP nm 38 32 29 27 22 18 17 15.3 14.0 12.8 11.7 10.7 9.7 8.9 8.1 7.4
Vdd V 1.05 1.05 1.05 1.00 0.95 0.95 0.95 0.85 0.85 0.85 0.85 0.75 0.75 0.75 0.75 0.75
EOT, Bulk nm 1.2 1.2 1.2 1 0.9…….. SOI 1 0.95 0.9 0.85 0.8…….. DG 1.1 1.1 1 1 0.9 0.9 0.8 0.8 0.7 0.7
100.90
1.00
1.10
1.20
Lg, nm
Vdd, V
HP ITRS 2009
7nm = Big Litho Challenge
ITRS 2009 : MAIN FEATURES (2)
14IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
10.40
0.50
0.60
0.70
0.80
2008 2010 2012 2014 2016 2018 2020 2022 2024 2026
EOT,nm
Bulk
SOI DG
0.6V = +/- OK
0.5nm = very HK and no pedestal SiO2 ?
Relaxation in EOT; Bulk–>SOI->DG
Kmob (mobilityimprovement) - 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8Kvs (saturation velocity impr.) - 1.10 1.11 1.11 1.12 1.13 1.13 1.14 1.15 1.15 1.16 1.17 1.17 1.18 1.19 1.20 1.20Kbal Idsat (imp. due to ballistictransport) - 1 1 1 1 1.06 1.12 1.19 1.26 1.34 1.42 1.50 1.59 1.69 1.79 1.90 2.01
Saturated !
Questionable !
Improbable !
Year 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024
HINT : WORK ON PMOS !!!
DIFFICULT TO BOOST CURRENT FURTHER
–YES, BUT IT ALREADY HAS BEEN +/- DONE !
15IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
~ X2.50
~ X1.14Data from Intel
In/Ip - 1.3 1.29 1.27 1.26 1.25 1.24 1.22 1.21 1.20 1.19 1.18 1.16 1.15 1.14 1.13 1.12
HINT : WORK ON PMOS !!! –YES, BUT IT ALREADY HAS BEEN +/- DONE !
ORTHOGONAL CHANGE DUE TO POWER CRISIS AND PERFORMANCE CRISIS
HP ROADMAPS
16IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
ITRS 2011 ?
Introduction
CMOS Technology Roadmap (ITRS) overview Density scaling (Gate length/pitch)Power scaling (low power/leakage) Voltage scaling
SOC requirements and prerogatives
OUTLINE
17IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
SOC requirements and prerogatives
Performance scaling – New insightBULKIII-V CHANNELSFINFETFDSOI
Variability for logic/for SRAM
Perspective
Some Digital/Analog Some Digital/Analog SoCSoC ExamplesExamplesSome Digital/Analog Some Digital/Analog SoCSoC ExamplesExamples
W. Krenik et al., IEEE JSSC (2005) (TI)
18IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
STMicroelectronics STM32 - 32bit µcontroller
W. Krenik et al., IEEE JSSC (2005) (TI)
Intel’s 45nm CoreTM i7 processor (Nehalem).F. Bœuf, 2009 VLSI SC
Main Elements of a Main Elements of a SoCSoCMain Elements of a Main Elements of a SoCSoC
High SpeedLogic
Critical LeakagePRCMU
eDRAMeNVM
Analog/RFRF ft,fmax,
matching, Noise
Extremely HighSpeed
in Burst mode
Static PowerVddRet as
Density, Process compatibility
High SpeedPdyn limited
19IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
PRCMU
High Voltage SRAM AreaLow Vdd op.
Vmin as low as possible
VddRet as low as possible
voltage, surfaceFt,Fmax,ESD
High Voltage Operation, data transfer
I/Os
F. Bœuf, 2009 VLSI SC
Introduction
CMOS Technology Roadmap (ITRS) overview Density scaling (Gate length/pitch)Power scaling (low power/leakage) Voltage scaling
SOC requirements and prerogatives
OUTLINE
20IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
SOC requirements and prerogatives
Performance scaling – New insightBULKIII-V CHANNELSFINFETFDSOI
Variability for logic/for SRAM
Perspective
IN
VDD
OUT
1
4
3
2
5
ττττ
2ττττ
0
34
5
76
1 2
ττττ2ττττ
0
Effective Effective CurrentCurrent ((IeffIeff) as ) as metricmetric of speedof speed
SWITCHING TRAJECTORY WHEN CHARGING /DISCHARGING THE LOAD
IDN
V =V /2
VGS=VDD2ττττ
Ion is NOT a speed indicator
21IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
IN OUT
CL
Vdd
Ref.: M.H. Na et al., IEDM 2002, p.121.
VDSVDD/2
VGS=VDD/2
0
ττττ
VDD
Ieff IS A GOOD SPEED INDICATOR
3
==+
===2
;;22
1 ddDddGddD
ddGeff
VVVVIVV
VVII
3
==+
===2
;;22
1 ddDddGddD
ddGeff
VVVVIVV
VVII
3
==+
===2
;;22
1 ddDddGddD
ddGeff
VVVVIVV
VVII
3
==+
===2
;;22
1 ddDddGddD
ddGeff
VVVVIVV
VVII
3
==+
===2
;;22
1 ddDddGddD
ddGeff
VVVVIVV
VVII
3
==+
===2
;;22
1 ddDddGddD
ddGeff
VVVVIVV
VVII
3
==+
===2
;;22
1 ddDddGddD
ddGeff
VVVVIVV
VVII
3
==+
===2
;;22
1 ddDddGddD
ddGeff
VVVVIVV
VVIIExample of CHARGING
IEFF IEFF dependsdepends on DIBL on DIBL ––NEW !!!NEW !!!
-
Long channel
- short
SCE – Short Channel EffectSCE
ID
same IonVdd
Techno w/o DIBL
Techno w. DIBL
22IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
- SCE DIBL
Vds
DIBL – Drain Induced Barrier Lowering
- shortchannel
VdVdd/2 Vdd
DIBL
Ieff w.DIBL< Ieff w/o DIBL
Vdd/2
600
800
1000
d (µA
)
150
11580DIBL=40
I2=810
I2=620
Ieff ≈≈≈≈(340+620)/2=480
Ieff ≈≈≈≈ (340+810)/2=575
∆f/f=∆Ieff/Ieff=95/480=20%
DIBL = NEW PERFORMANCE DRIVER
23IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
0 0.2 0.4 0.6 0.8 10
200
400
Vd (V)
I d
Collboration STMicroelectronics & L. Wei, P. Wong (Stanford U.)
(*) in this example, all device have the same Ion, Ioff and capa environement
I1=340
=20%
Lower DIBL =
Higher Performance
23
Inverter Speed (using IEFF current)
Iso-performance curves are more sensitive to DIBL for (HVT) high-Vth and/or low VDD
Ion
(µ
A/µ
m)
HVT Device
LVT Device
500
1200
Low Vdd / High VT
High Vdd / Low VT
( )thdd VV
DIBL
f
f
−∆−=∆ 2
24IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
For High Performance (LVT) devices, DIBL is a less important performance factor
Ion
(µ
A/µ
m)
DIBL (V)
Ion
(µ
A/µ
m)
DIBL (V)
Ref.: Lan Wei et al., SSDM 2009, ST-Stanford common paper
50 200300
DIBL (mV)
50 200DIBL (mV)900
Introduction
CMOS Technology Roadmap (ITRS) overview Density scaling (Gate length/pitch)Power scaling (low power/leakage) Voltage scaling
SOC requirements and prerogatives
OUTLINE
25IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
SOC requirements and prerogatives
Performance scaling – New insightBULKIII-V CHANNELSFINFETFDSOI
Variability for logic/for SRAM
Perspective
DSel
dep
el
ox
el
j
ox
Si VL
T
L
T
L
XDIBL
+=
2
2
180.0εε
WHY DOES THE PLANAR MOSFET FAIL ?(Ref.: T. Skotnicki, et al., Electron Device Letters, Vol 9, N° 3, 1998)
Suppose : Lel=2/3Lg
26IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
REF.: T. Skotnicki, invited paper ESSDERC 2000, pp. 19-33, edit. Frontier Group
Tdep=1/2Lg
Xj=1/2Lg
mVV 1401 43
201
4
31 4.2
2
2
=
+
Suppose : Lel=2/3Lg
BULK :Increasing SCE and DIBL for Logic, and Variability for SRAM imply stagnation in Lgate scaling down
Area problem – to scale pitch with constant Lgate -contacts are dangerously approaching gate leading to techno difficulties and performance compromise due to increasing gate to contact capacitance
27IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
Constant Lgate and increasing capacitance lead to saturation in performance growth, also due to stagnation in strain technologies
L C
Main Mobility Enhancement Techniques
SixGe1-x
SSOI
Tensile bi-axial
SubstrateSubstrate--basedbased ProcessProcess--basedbased
Crystal/Channel
Bulk SOI
Natural µ enhancement
eSiGe
Comp.
SEG
eSiC
Tensile
Gate
Replac. Gate
Tensile
MEOL
Contact
Tensile
Liners
CESL SMT
Tensile Tensile
28IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
nMOS+pMOS
SSOI Channel Orient. Substrate Orient.
<100>
(110)
pMOS pMOS nMOS nMOS
pMOS
Compressive
nMOS nMOS nMOS
pMOS
Compressive
SPEED Race w. Bulk Impossible !MoreSpeed
MoreMOS
Current
LessRC
Mobility Lg Reduce ReduceEOTVdd
New Transistor Structure
29IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
Mobility-Strain
Boosters
Lgfaster
scaling
ReduceMetal
resistance
ReduceCapacitance
Si +/- none !III-V ?
EOTfasterscaling
VddOver-drive
NOSince Pdyn
New HKNot ready
Igate !
No lithoIoff, DIBLVariabilit
RatherIncreases !
RatherIncreases !No new LKavailableSOI
FinFETNanowires
Introduction
CMOS Technology Roadmap (ITRS) overview Density scaling (Gate length/pitch)Power scaling (low power/leakage) Voltage scaling
SOC requirements and prerogatives
OUTLINE
30IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
SOC requirements and prerogatives
Performance scaling – New insightBULKIII-V CHANNELSFINFETFDSOI
Variability for logic/for SRAM
Perspective
Published Data : Mobility
Company Type Mobility vs Si Lgate min
IMEC Ge (100) P MOSFET x2.2 65nm
LETI/ST Ge (100) P MOSFET X2.8 75nm / 30nm (tbp)
Stanford University Ge (111) N MOSFET x1.5 100µm
Tokyo University Ge (111) N MOSFET x1.5 300µm
IMEC InGaAs MOSFET x4x2
10µm1.5µm
31IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
SEMATECH InGaAs MOSFET X4 5µm
Singapore University InGaAs MOSFET x2 95nm
Purdue University InGaAs MOSFET No data 160nm
Purdue University InGaAs FINFET No data 100nm
Tokyo University InGaAs-OI MOSFET x1.35 500µm
SEMATECH InGaAs QWFET X9 (Hall) 5µm
IBM InGaAs QWFET No data 90nm
INTEL InGaAs QWFET >10 (Hall) 75nm
Limiting Velocity in Transistor Channel
2.3
2.8
3.3E
ffe
ctiv
e S
atu
rati
on
Ve
loci
ty (
10
7 c
m/s
)InGaAS MOSFET
Strained-Si nMOSFET
Ge pMOSFET
Strained-Si pMOSFET
32IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
0.8
1.3
1.8
0 20 40 60 80 100
Eff
ect
ive
Sa
tura
tio
n V
elo
city
(1
0 7
cm
/s)
Gate Length (nm)Data : F. Bœuf
Darkspace in III-V Materials
1.6
2.0
Cap
aciti
ve e
quiv
alen
t th
ickn
ess
(nm
)
1.6
2.0
Cap
aciti
ve e
quiv
alen
t th
ickn
ess
(nm
)
InGaAs
Parabolic bandstuctureNon- Parabolic bandstucture
Due to lower DOS, DS is bigger in III-V materials. Still, DS value dependson the non-parabolocity factor of the conduction band More research is needed to correctly describe this effect
33IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
0.0 4.0x1012 8.0x10120.0
0.4
0.8
1.2
Cap
aciti
ve e
quiv
alen
t th
ickn
ess
(nm
)
Inversion density (cm-3)0.0 2.0x1012 4.0x1012 6.0x1012 8.0x1012 1.0x1013
0.0
0.4
0.8
1.2
Cap
aciti
ve e
quiv
alen
t th
ickn
ess
(nm
)
Inversion density (cm-3)
From Q. Raphay, IMEP, unpublished material
InGaAs
GaAsSi, GeInGaAs
GaAs
Si, Ge
+3~4A +5~6A
+10A
+3~4A
High µ/vsat ~ Small Eg ~ High εεεε
SemiconductorEff. Electr
on mass
Bandgap(eV) at 300K
Dielectricconstant
Electron bulk mobility (cm2/Vs)
Saturation velocity
(107 cm/s)
InSb 0.014 0.17 15.9 77000 5
InAs 0.023 0.36 12. 30000 3.5
GaSb - 0.68 14.8 5000 -
34IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
InP - 1.27 12.1 4500 -
GaAs 0.063 1.43 11.5 8000 1.2
Ge 1.59/0.081 0.66 16 3600 0.6
Si 0.98/0.19 1.12 12 1350 1
Virtual III-V (~InGaAs) : µeff X10, vsat X3, εεεε X1.25, Tinv +2 upto +6.5Å
How do ε & Dark Space impact DIBL and SS in III-V’s (1)
DS
el
dep
el
inv
el
j
ox
Si VL
T
L
T
L
XDIBL
+=
2
2
180.0εε
Tinv=Tox+DS.εox/εsB
DSidep qN
Tφε2=
35IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
elelelox LLL ε
( )
Φ+
+++=
d
DS
el
dep
el
j
el
inv
ox
Si
dep
inv
ox
Si V
L
T
L
X
L
T
T
T
q
kTSS 1
4
31110ln
εε
εε
[8] T. Skotnicki et al., IEEE Trans. On Elec. Dev., Vol.55 ,Issue 1, pp 96-130, 2008
250
300
350
400
DIB
L (m
V)
epsilon +3 (+25%)Tinv+6.5A (+59%)Reference (Si)
100
110
120
130
dec)
epsilon 15
(+25%)
Tinv+6.5A
How do ε & Dark Space impact DIBL and SS in III-V’s (2)
36IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
(b)
0
50
100
150
200
10nA/µm 100nA/µm 2µA/µm
DIB
L (m
V)
Ioff (nA/µm)
60
70
80
90
100
SS (m
V/d
ec
(+59%
Reference
(Si)
(b)
Cumulative impact of the constructive and destructive effects for constant Ioff=10nA/µm, 22nm CMOS
IdealIII-V
+15%+23%
+25%
+53%
-22%
-18%
-12%
-42%
SSi
+49%
III-V w/ relaxed L
-29%
37IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
Si Ref SSi
III-V
-42%
-55%
« III-V w/ relaxed L » – so as to remove penalty due to larger DIBL and SS
Step-by-Step High-µ Material Analysisfor 16nm node at Ioff = 0.5nA/µm
35
40
a.u
.)
Material Epsilon Kvs Kµ DS (nm) remark
S-Si (n) 12 1.7 1.8 +0.3 Full Strain-Si
S-Si (p) 12 1.5 7 +0.5 Full Strain-Si
UTB 12 1.1 1.2 +0.3 Slightly Strained
Virtual III-V 13.8 >3 10 +0.5 High µ for electron
Ge 16 1.5 3 +0.5 High µ for holes
38IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
0
5
10
15
20
25
30
Silicon
Lg=18nm
Strained – Si
Lg=18nm
High µ/velocity
Lg=16nm
Epsilon=13.8
Lg=16nm
DS +0.2nm
Lg=16nm
Relaxed NFET to 22nm
NA
ND
2 (
FO
3)
Fre
qu
en
cy (
a.u
BulkSi – Ref.BulkSi – Ref.
BulkS-SiBulkS-Si
Ideal III-V/ GeIdeal III-V/ Ge
RealIII-V/ GeRealIII-V/ Ge
RelaxedIII-V/ GeRelaxedIII-V/ Ge
III-V/ GeIII-V/ Ge
Introduction
CMOS Technology Roadmap (ITRS) overview Density scaling (Gate length/pitch)Power scaling (low power/leakage) Voltage scaling
SOC requirements and prerogatives
OUTLINE
39IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
SOC requirements and prerogatives
Performance scaling – New insightBULKIII-V CHANNELSFINFETFDSOI
Variability for logic/for SRAM
Perspective
FinFET - STATE OF THE ART
FinFET structure in a dense array with
FinFET
Source
Drain
40IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
CPPFinPitch
IBM Allience , Albany 2010
FinFET structure in a dense array with CPP=80nm and Fin pitch = 50nm
DSel
dep
el
ox
el
j
ox
Si VL
T
L
T
L
XDIBL
+=
2
2
180.0εε
WHY THE Double-Gate DOES NOT FAIL ?(Ref.: T. Skotnicki, et al., Electron Device Letters, Vol 9, N° 3, 1998)
Suppose : Tsi=1/3Lg & Lel=2/3LgXj=1/2Tsi
41IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
REF.: T. Skotnicki, invited paper ESSDERC 2000, pp. 19-33, edit. Frontier Group
mVV 321 41
201
12
31 4.2
2
2
=
+
Suppose : Tsi=1/3Lg & Lel=2/3LgXj=1/2Tsi
Tdep=1/2Tsi
Xj=1/6Lg
Tdep=1/6Lg
Tsi=1/3Lg Impossible, suppose limited to 12nm =>
ELECTROSTATICS FINFET(1) – vs – UTBB SOI:FinFET – COMMON GATES
=>BB IMPOSSIBLEFinFET
after ROTATIONFDSOI-
Utra Thin BOX
42IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
DSel
dep
el
ox
el
j
ox
Si VL
T
L
T
L
XDIBL
+=
2
2
180.0εε
Tdep=Tsi/2
Xj=Tsi /2
Tsi ≥ 12nm
Tox = 1nm
Tbox = NONE
Tdep=Tsi+λTbox
Xj=Tsi
Tsi ≥ 6nm
Tox = 1nm
Tbox = 10nm
Lel=16nm, λ≈0.3
≥51mV
Vds=0.8V
≥77mV
ELECTROSTATICS FINFET (2) – vs – UTBB SOI:FinFET – SEPARATE GATESBAD ELECTROSTATICS !!!
FinFETafter ROTATION
FDSOI-Utra Thin BOX
BB – STILL IMPOSSIBLE
43IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
DSel
dep
el
ox
el
j
ox
Si VL
T
L
T
L
XDIBL
+=
2
2
180.0εε
Tdep=Tsi+λTbox
Xj=Tsi
Tsi ≥ 12nm
Tox = 1nm
Tbox = Tox
Tdep=Tsi+λTbox
Xj=Tsi
Tsi ≥ 6nm
Tox = 1nm
Tbox = 10nm
Lel=16nm, λ≈0.3
≥144mV
Vds=0.8V
≥77mV
BB – STILL IMPOSSIBLEIF MORE THAN 1 Fin
…… AND BB STILL IMPOSSIBLE , see next slide
FinFET’s INCOMPATIBILITY W. BODY-BIAS
FDSOI = 2D FinFET w. COMMON GATE
gate
drain
Thin Silicon film
FinFET w. SEPARATE GATES
LOST ADVANTAGE IN DIBL !
gate
drain
Lg
44IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
gate
source
Body-BiasAs on Bulk
Body-BiasSince
GATE=BACK-BODY
gate
source
Lg
Body-Bias
SinceGate(N+1)=Body(N)
And NO ROOM for CONTACTS
Fin1 2 3 4
Introduction
CMOS Technology Roadmap (ITRS) overview Density scaling (Gate length/pitch)Power scaling (low power/leakage) Voltage scaling
SOC requirements and prerogatives
OUTLINE
45IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
SOC requirements and prerogatives
Performance scaling – New insightBULKIII-V CHANNELSFINFETFDSOI
Variability for logic/for SRAM
Perspective
FDSOI FDSOI devicesdevices on SOI Waferson SOI Wafers
K. Cheng et al., VLSI 2009 (IBM)Krivokapic et al., IEDM
2002(AMD)
M. Fujiwara et al., IEEE SOI Conference 2005 ( Toshiba)C. Fenouillet-Beranger et
al., unpublished
46IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
N.Sugii et al., IEDM 2008 (Hitachi)
« SOTB»DST
R.Chau et al., IEDM 2001(Intel)
Hybrid FDSOI
C. Fenouillet-Beranger et al., IEDM 2009(ST/LETIl)
al., unpublished(ST/LETIl)
0.
FDSOI BULK
DSel
dep
el
ox
el
j
ox
Si VL
T
L
T
L
XDIBL
+=
2
2
180.0εε
WHY DOES THE UTB SOI/SON DO BETTER ?(Ref.: T. Skotnicki, et al., Electron Device Letters, Vol 9, N° 3, 1998)
Suppose : Tsi=1/3Lg & Lel=2/3Lg
47IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
REF.: T. Skotnicki, invited paper ESSDERC 2000, pp. 19-33, edit. Frontier Group
Xj=Tsi
mVV 751 21
201
2
11 4.2
2
2
=
+
Suppose : Tsi=1/3Lg & Lel=2/3LgTdep=Tsi
Xj=1/3Lg
Tdep=1/3Lg
Gate
Saddle point: reveals strong DIBL
Gate
No Saddle point !
BOX = 10nm
Source Drain Source Drain
Why thin BOX?
48IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
BOX = 100nm BOX = 10nm
Electrostatic potentialThin BOX can suppress the lateral electrostatic coupling between Drain and Channel
Drain-to-ChannelCoupling via BOX
REF.: T. Skotnicki et al., ECS Symp, SOI Techn. & Dev XI, edit S. Cristoloveanu , 2003
NO Coupling to channel via BOX
2030405060708090
DIB
L(m
V)
NMOS FDSOITox 1nm Vdd 1VTsi 5nm Lg 30nm
Lg 40nm
Closed symbol: TCAD simulation
ElectrostaticsElectrostatics of UTB SOIof UTB SOIT. Skotnicki et al. IEEE EDL, March’88 & IEDM’1994
XjTdep
Bulk
T
Sij
TTT
TX
λ+→
→
DSel
dep
el
ox
el
j
ox
Si VL
T
L
T
L
XDIBL
+=
2
2
180.0εε
C.Fenouillet-Beranger, et al., SOI Conference 2003
49IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
010
0 20 40 60 80 100 120 140 160Tbox(nm)
Closed symbol: TCAD simulationOpen symbol: MASTAR
TBOX
TSi boxSidep TTT λ+→
box
el
el
box
el
box
T
L
L
T
L
Ttgh
+
−+= 09.01150.1121.0λ
UTBDS
el
boxSi
el
ox
el
Si
ox
Si VL
TT
L
T
L
TDIBL
λεε +
+=
2
2
180.0
Body Bias – Powerful booster
pMOSnMOS
As
AsAsBOX
In
B B
B
Vb=0Vb=FBBVb=RBB
Vb=VddVb=FBBVb=RBB
BOXAs
Normalspeed+20% (1/2 amplit.)
Pstat / 3 (1/2 amplit.)
Full Amplitude RBB and FBB
50IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
Vsub(p)=0
np
FBB – Forward Body BiasRBB – Reverse Body Bias
Full Amplitude RBB and FBB
Multi-VT capability with 2 Metals
0
0,2
0,4
0,6
0,8
Th
resh
old
vo
ltag
e (V
)
LVT RVT HVT SHVT
GP-N GP-P
GP-PGP-N
nMOS
BOX
TiN
nMOS
BOX
TaAlN
pMOS
N-GP P-GP
BOX
TiN
nMOS
BOX
TaAlN
pMOS
P-GP N-GP
Metal change
GP change
LVT
RVT
BOX
TiN
nMOS
BOX
TaAlN
pMOS
N-GP P-GP
BOX
TiN
nMOS
BOX
TaAlN
pMOS
P-GP N-GP
Metal change
GP change
LVT
RVT
nMOS pMOSnMOS pMOSnMOS pMOS
Logic SRAM DRAM
51IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
Large range of VTs for SoC are possible on FDSOI w/o SiGe (contrarily to bulk) and with a dual gate approach (similarly as for bulk)
-0,8
-0,6
-0,4
-0,2
0
Th
resh
old
vo
ltag
e (V
)
GP-P GP-NGP-NGP-P
pMOSGP change metal
change
TiN TaAlN/TaN
BOX
nMOS
BOX
TaAlN
pMOS
N-GP P-GP
BOX
nMOS
BOX
TaAlN
pMOS
P-GP N-GP
TiN
TiN
HVT
SHVT
BOX
nMOS
BOX
TaAlN
pMOS
N-GP P-GP
BOX
nMOS
BOX
TaAlN
pMOS
P-GP N-GP
TiN
TiN
BOX
nMOS
BOX
TaAlN
pMOS
N-GP P-GP
BOX
nMOS
BOX
TaAlN
pMOS
P-GP N-GP
TiN
TiN
HVT
SHVT
Body Bias with UTBOX =>+20% in speed (FBB) and Pstat/3 (RBB)
0
0.2
0.4
0.6
-1.5 -1 -0.5 0 0.5 1 1.5
VB (V)
VT (V) LG=18nm
VD=0.05V
TBOX=10nm
52IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
Good back bias capability with both N-type or P-type GPs That remains true even with very short MOSFETs (18nm !)
-0.6
-0.4
-0.2
-1.5 -1 -0.5 0 0.5 1 1.5
PMOS w p-type GP
PMOS w n-type GP
NMOS w p-type GP
NMOS w n-type GP
11nm7nm
I/O devices for ESD protectionsI/O devices for ESD protectionsI/O devices for ESD protectionsI/O devices for ESD protections
Circuit to be
protected
Trigger Circuit
Vdd
gnd
IOIO11 IOIO22
ESD devices types:
53IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
ESD Commitments: Transparency (DC) and Robustness for ESD (typical ESD Commitments: Transparency (DC) and Robustness for ESD (typical values ~100ns& 1values ~100ns& 1--2 A))2 A))
Best cases: at same robustness, less areaBest cases: at same robustness, less area
PWELL
N+P+ STIP+
N+ P+NWELL
gate P+
N+ PWELL
gate
N+
STI diodeSTI diode gated diodegated diode MOS transistorMOS transistor
ESD devices types:
Gated Diodes / ESD are critical in FDSOIGated Diodes / ESD are critical in FDSOIGated Diodes / ESD are critical in FDSOIGated Diodes / ESD are critical in FDSOI
T.Benoist et al, EOS/ESD Symposium, 2010
Bulk gated diodes without HKMG
width Ron(Ω) It2 (mA/um)
10 x (2.5 um) 1.78 12
10 x ( 5 um) 1.08 11
10 x (10 um) 0.72 11
40 x (5 um) 0.32 10
FDSOI gated diodes with HKMG
54IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
FDSOI gated diode
Breakdown current is Breakdown current is divided by 4 vs Bulk!divided by 4 vs Bulk! Robustness (breakdown current It2) and Resistance On
(Ron) for FDSOI gated diodes
FDSOI gated diodes with HKMG
width Ron(Ω) It2 (mA/um)
10 x (2.5 um) 16 2.8
10 x ( 5 um) 7.8 2.5
10 x (10 um) 4.2 2.4
40 x (5 um) 2.7 2.2
On FDSOI, the area of ESD protections (as based on gated-diodes) would need to by increased X4 !!! SOLUTION=COINTEGRATION =>
Protection layer Si +BOX removal
Easy CoEasy Co--Integration Integration of FDSOI with Bulk (thin BOX)of FDSOI with Bulk (thin BOX)Easy CoEasy Co--Integration Integration of FDSOI with Bulk (thin BOX)of FDSOI with Bulk (thin BOX)
SOI
FDSOI
55IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
UTBB area Bulk areaC. Fenouillet et al., IEDM 2009 (ST/LETI )
FDSOI BULK
HK dielectric
Metal electrode
HK dielectric
Metal electrodeThick Oxide
Dual Gate Oxide Integration with HK/MG on FDSOIDual Gate Oxide Integration with HK/MG on FDSOIDual Gate Oxide Integration with HK/MG on FDSOIDual Gate Oxide Integration with HK/MG on FDSOI
56IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
K.Cheng et al, IEDM09
C. Fenouillet et al., IEDM 2009 (ST/LETI )
Very Good UTB-FDSOI Analog Properties
1
10
100
1000
0,01 0,1 1
An
alo
g ga
in, G
m/G
d
Bulk [2]
UTB [1]
Analog Performance
G=30@5Lmin
1
10
100
1000
An
alo
g g
ain
, Gm
/Gd
I/O
UTB [1]
Analog Precision
G=100@10Lmin
Bulk
FDSOI
Bulk
FDSOI
57IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
0,01 0,1 1
Lg(µm)
1
0,1 1 10
Lg (µm)
0
50
100
150
200
250
300
350
400
0 100 200 300
Fmax
(GH
z)
Lgate (nm)
Bulk Silicon Data (Lit.)ITRSUTBFinFET
0
50
100
150
200
250
300
350
400
450
500
10 100
FT
(GH
z)
Lgate (nm)
Bulk&PDSOI Data (lit.)
ITRS
FDSOI
FinFET FDSOI
UTBB SOI scalability to node 11nm and beyond
• TCAD extrapolation for channel Si thickness
• Model is calibrated on Si dataBOX=50nm
Lg=
10nm
58IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
O. Faynot et. al. FDSOI Workshop Oct. 15, 2009; Courtesy of CEA-LETI
BOX scaling is an additional weapon of FDSOI BOX scaling enables FDSOI scalability even beyond node
11nm with TSi no thinner than ~ 6-7nm This leaves a comfortable margin w/r to Quantum Realm
QUANTUM REALM
Introduction
CMOS Technology Roadmap (ITRS) overview Density scaling (Gate length/pitch)Power scaling (low power/leakage) Voltage scaling
SOC requirements and prerogatives
OUTLINE
59IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
SOC requirements and prerogatives
Performance scaling – New insightBULKIII-V CHANNELSFINFETFDSOI
Variability for logic/for SRAM
Perspective
DSel
dep
el
ox
el
j
ox
Si VL
T
L
T
L
XDIBL
+=
2
2
180.0εε
Tdep=3/4Lel
WHO DOES BETTER w. DIBL THAN BULK DOES ??(Ref.: T. Skotnicki, et al., Electron Device Letters, Vol 9, N° 3, 1998)
Xj=3/4LelBULK
III-V
Tox +2A
+15%
140mV/V
εεεεsi
210mV/V
Log(Id)
Vg
DIBL
Vdd0.1V
60IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
Tdep=Tsi/2
Xj=Tsi/2
Tsi ≥ 10nm
FDSOI
FinFET
Tdep=Tsi+λTbox
Xj=Tsi ≥6nm
80mV/V
70mV/V
ETSOI
UTBB
110mV/V
Tdep=3/4Lel
WHO DOES BETTER THAN BULK w. Pstat??(Ref.: T. Skotnicki, et al., IEEE TED, pp. 96-130, Jan. 2008
Xj=3/4Lel
BULK
III-V
Tox +2A
+15%
Pstat=Nx
10nA/µmxVdd(S=95 mV/dec)
εεεεsi
Φ+
+++=
d
ds
el
dep
el
j
el
ox
ox
Si
ox
dep V
L
T
L
X
L
T
C
C
q
kTS 21
4
311)10ln(
εε
Pstat X5(S=110mV/dec)
S –SubthresholdSlope
Log(Id)
Vg
61IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
RBB =>Pstat /3
Tdep=Tsi/2
Xj=Tsi/2
FDSOI
FinFET
Tdep=Tsi+λTbox
Xj=TsiETSOI
UTBB
Vg
Pstat /3(S=85mV/dec)
Pstat /15(S=75mV/dec)
Pstat /10(S=65mV/dec)
80
100
120
140
160IN
V (
FO
1)
Fre
qu
en
cy (
a.u
.)
L=26nmw/stressors
L=20nmNo stressors
L=20nmNo stressors
L=20nmNo stressors
20L
P U
TB
B w
/ FB
B
20L
P U
TB
B w
/ Ful
l FB
B
L=20nmNo stressors
L=20nmNo stressors
Reduced DIBL and FBB (Forward-Body Bias) provide the winning solution with FDSOI @ 20nm
Vdd=0.9V FDSOI
20L
P F
INF
ET
feas
ible
62IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
0
20
40
60
BULK 20LP ETSOI UTBB UTBB/FBB UTBB/F-FBB FinFET
INV
(F
O1
) F
req
ue
ncy
(a
.u.)
Technology
20L
P B
UL
K
20L
P E
TSO
I
20L
P U
TB
B
20L
P U
TB
B w
/ FB
B
20L
P U
TB
B w
/ Ful
l FB
B
Tsi=10nmTbox=145nm
Tsi=6nmTbox=25nm
20L
P F
INF
ET
Not
yet
feas
ible
Tsi=5nmTbox=145nm
Tsi=6nmTbox=25nm
Tsi=6nmTbox=25nm
Dynamic Power @ constant Frequency, 20nm node
0.6
0.8
1
1.2
No
rma
lize
d D
yn
ma
nic
PO
we
r IN
V (
FO
1)
Vdd=0.9V
Vdd=0.8V Vdd=0.79V
Vdd=0.74V Vdd=0.68V
20nm LP CMOS Same Frequency = F(Bulk 20LP)
-40% Pdyn-55% Pdyn
63IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
0
0.2
0.4
0.6
BULK 20LP ETSOI UTBB UTBB/FBB UTBB/F-FBB FinFET
No
rma
lize
d D
yn
ma
nic
PO
we
r IN
V (
FO
1)
Technology
Vdd=0.74V
Vdd=0.66V
Vdd=0.68V
DG
Bulk /w strain
Single Gate FDSOI
Multigate Gate UTBVdd=0.8V
16nm
UT
BB
w/ F
BB
Reduced DIBL along w. FBB (Forward-Body Bias) provide the winning solution with FDSOI @ 16nm
64IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
20L
P@0.
9V
16L
P
16nm
ET
SOI
16nm
UT
BB
16nm
Pla
nar
DG
16nm
Fin
FET
22/1
8nm
Hig
h-µ
16nm
UT
BB
w/ F
BB
III-V / Ge Bulk
relaxed Lg Tsi=4nmTbox=145nm
Tsi=6nmTbox=10nm Tsi=6nm
Tbox=10nm
Tsi=10nmTbox=145nm Tsi=10nm
Tbox=145nm
Dynamic Power Dissipation @ constant frequency, 16nm
0.6
0.8
1
1.2N
orm
aliz
ed
Pd
yn
(FO
1)
@ 2
5%
sp
ee
d im
pro
vem
en
t Vdd=0.9V
Vdd=0.88V
Vdd=0.81V
Same Frequency = F(20LP) + 33%
65IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
0
0.2
0.4
0.6
BULK 20LP BULK III-V / Ge
Bulk
ETSOI UTBB UTBB w/F-
FBB
DG FinFET
No
rmal
ize
d P
dyn
(F
O1
) @
25
% s
pe
ed
imp
rove
me
nt
Technology
Vdd=0.81V
Vdd=0.79VVdd=0.8V
Vdd=0.67V
Vdd=0.69V Vdd=0.69V
Introduction
CMOS Technology Roadmap (ITRS) overview Density scaling (Gate length/pitch)Power scaling (low power/leakage) Voltage scaling
SOC requirements and prerogatives
OUTLINE
66IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
SOC requirements and prerogatives
Performance scaling – New insightBULKIII-V CHANNELSFINFETFDSOI
Variability for logic/for SRAM
Perspective
44 3
2
4ch
el
ox
ox
Fsth N
WL
TqV
εϕε
δ =
8k-MOSFET ARRAY, Tox=11nm, Nch=7.1e16cm-3
VARIABILITY - FLUCTUATIONS:
A 4.2 nm MOSFET in production 2023
67IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
T. Mizuno et al., IEEE TED, Nov. 1994Courtesy of A. Asenov, Glasgow Univ., UK
Electron concentration
Line Edge Roughness (LER)and Poly Grains (PGG) vs RandomDopant Distribution (RDD) – RDD is the dominant effect !
68IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
Courtesy Prof. A. Asenov Glasgow U.
A. Cathignol et al. , EDL, 2008 (ST)
Fluctuations –IMPACT ON LOGIC and on SRAM
SNM w/o process spread
Microelectronics Journal 36 (2005) 789–800Huifang Qin
LWA
LWT
NqV vtox
ox
dcsth
112
0
4 30 ≡
Φ=
εεεε
δ
69IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
SNM with process spread
Courtesy Prof. A. Asenov
LESS VARIABILITY W. SOI - EXPLANATION:
70IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
σVt(SOI)/ σVt(Bulk)
=(NaSOI/NaBulk)1/4
=(1/100)1/4
≈ 1/3Ref.: Denis Flandre, UCL Louvain-La-Neuve, BE
CONTINUITY OF SRAM SIZE SCALING:
71IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
F. Bœuf, 2009 VLSI SC
SRAM: Minimum Operating Voltage SRAM: Minimum Operating Voltage
VminVmin depends strongly on the depends strongly on the nMOSnMOS& & pMOSpMOS Vt’sVt’s
– Variation in VtN or VtP will cause strong Vmin degradation, i.e. non functionnal SRAM circuit
– Statistical dispersion of VtN and VtP can cause circuit fails (due to SNM/WM dispersion)
WriteFail
ReadFail
∆Vt
∆Vt
72IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
to SNM/WM dispersion)
N.Planes et al., SSDM 2008
Fail
P. Stolk at al., T-ED 1998 (NXP)Conflict with electrostatics when
L shrink
Conflict when Area shrink
Conflict with cell-leakage
F. Bœuf, 2009 VLSI SC
SMALL IS DIFFICULT
Bulk_poly_0.276µm2
PU W/L= 55/80PD W/L=215/55PG W/L=170/65
in nm0.6
0.8
1.0
Vou
t (re
sp. V
in)
Bulk_poly_0.276µm2
PU W/L= 55/80PD W/L=215/55PG W/L=170/65
in nm0.6
0.8
1.0
Vou
t (re
sp. V
in)
Bulk_poly_0.164µm2Bulk_poly_0.164µm2Bulk_poly_0.211µm2Bulk_poly_0.211µm2
73IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
0.0
0.2
0.4
0.6
0.0 0.2 0.4 0.6 0.8 1.0
Vin (resp. Vout)
Vou
t (re
sp. V
in)
0.0
0.2
0.4
0.6
0.0 0.2 0.4 0.6 0.8 1.0
Vin (resp. Vout)
Vou
t (re
sp. V
in)
0.0
0.2
0.4
0.6
0.8
1.0
0.0 0.2 0.4 0.6 0.8 1.0
Vin (resp. Vout)V
ou
t (r
esp
. Vin
)
Bulk_poly_0.164µm2
PU W/L= 45/32PD W/L=105/32PG W/L= 90/45
in nm
0.0
0.2
0.4
0.6
0.8
1.0
0.0 0.2 0.4 0.6 0.8 1.0
Vin (resp. Vout)V
ou
t (r
esp
. Vin
)
Bulk_poly_0.164µm2
PU W/L= 45/32PD W/L=105/32PG W/L= 90/45
in nm
0.0
0.2
0.4
0.6
0.8
1.0
0.0 0.2 0.4 0.6 0.8 1.0
Vin (resp. Vout)
Vou
t (re
sp. V
in)
Bulk_poly_0.211µm2
PU W/L= 55/45PD W/L=150/45PG W/L=120/55
in nm
0.0
0.2
0.4
0.6
0.8
1.0
0.0 0.2 0.4 0.6 0.8 1.0
Vin (resp. Vout)
Vou
t (re
sp. V
in)
Bulk_poly_0.211µm2
PU W/L= 55/45PD W/L=150/45PG W/L=120/55
in nm
After: T. Skotnicki et al. Innovative materials, devices and CMOS technologies for low-power mobile multimedia, pp. 96-130, IEEE TED, Jan. 2008
VDD=1.1V
0.6
0.8
1.0
1.2
Vo
ut (
resp
. Vin
)
VDD=1.1V
0.6
0.8
1.0
1.2
Vo
ut (
resp
. Vin
)
VDD=0.9V
0.6
0.8
1.0
1.2
Vo
ut
(res
p. V
in)
VDD=0.9V
0.6
0.8
1.0
1.2
Vo
ut
(res
p. V
in)
VDD=0.7V
0.6
0.8
1.0
1.2
Vo
ut
(res
p. V
in)
VDD=0.7V
0.6
0.8
1.0
1.2
Vo
ut
(res
p. V
in)
LP IS DIFFICULT
74IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
0.0
0.2
0.4
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Vin (resp. Vout)
Vo
ut (
resp
. Vin
)
0.0
0.2
0.4
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Vin (resp. Vout)
Vo
ut (
resp
. Vin
)
0.0
0.2
0.4
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Vin (resp. Vout)
Vo
ut
(res
p. V
in)
0.0
0.2
0.4
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Vin (resp. Vout)
Vo
ut
(res
p. V
in)
0.0
0.2
0.4
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Vin (resp. Vout)
Vo
ut
(res
p. V
in)
0.0
0.2
0.4
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Vin (resp. Vout)
Vo
ut
(res
p. V
in)
After: T. Skotnicki et al. Innovative materials, devices and CMOS technologies for low-power mobile multimedia, pp. 96-130, IEEE TED, Jan. 2008
2005 2007 2010 2013 2016 2019
Tolerable Die Fail 0.0001 0.0001 0.0001 0.0001 0.0001 0.0001
Memory Size(Mbits) 8 16 32 64 128 256
Tolerable Bit Fail 1.25E-11 6.25E-12 3.13E-12 1.56E-12 7.81E-13 3.91E-13
Required SNM/σσσσSNM 6.8 6.85 6.95 7 7.15 7.25
SRAM: Minimum Operating Voltage SRAM: Minimum Operating Voltage
75IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
Vmin reduction
BULK
Avt ~ 3.3 Vdd,nom=0.9V
0
1
2
3
4
5
6
0 1 2 3 4 5 6 7 8
Avt
(mV.
µm
)
Tox (nm)
Bulk
UTB
World record by LETI !
O. Weber et al. IEDM 2008 (LETI)
Variability and LP SRAM:
Data : F. Bœuf
76IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
1
1 1.2 1.4 1.6 1.8 2
Vmin
(V)
AVt (mV.µm)
FD
SOI
Vmin~0.6V
Bul
kVmin~0.75V
FDSOI/UTBOXAvt ~ 1.4
Vdd,nom=0.9V
Bulk: Avt = 2FDSOI: Avt = 1.4
Introduction
CMOS Technology Roadmap (ITRS) overview Density scaling (Gate length/pitch)Power scaling (low power/leakage) Voltage scaling
SOC requirements and prerogatives
OUTLINE
77IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
Performance scaling – New insightBULKIII-V CHANNELSFINFETFDSOI
Variability for logic/for SRAM
Perspective
PERSPECTIVEAll rational reasonings indicate that 15nm CMOS (at
least the 14nm LP) should switch from Bulk to UTBB (Ultra Thin Body and BOX) SOI
Once this accomplished, UTBB will remain the principal platform for 2-3 generations, since itsscalability (thanks to thin BOX) is very good, similar to
78IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
scalability (thanks to thin BOX) is very good, similar to that of FinFET
For further nodes, scaling may stop and thus renderperformance increase with high-µ materials (e.g. III-V) more efficient, as these materials manifest theiradvantage only with relaxed geometry (n-1 withrespect to n)
TO KNOW MORE :
T. Skotnicki et al. Innovative materials, devices and CMOS technologies for low-power mobile multimedia, pp. 96-130, IEEE TED, Jan. 2008
79IEDM 2010 Short Course • CMOS Technologies – Trends, Scaling and IssuesThomas Skotnicki
MASTAR , ITRS web page, http://www.itrs.net/models.html