Post on 15-Aug-2020
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CHAPTER 5
ATPG FOR CROSSTALK DELAY FAULTS USING
MULTI- OBJECTIVE GENETIC ALGORITHM
5.1 INTRODUCTION
Many real engineering problems involve simultaneous optimization
of multiple objectives such as cost, reliability and power consumption.
Optimization of such multiple objective problems is a procedure of finding
and comparing feasible solutions until no better solution can be found. One
solution cannot be termed as an optimum solution to multiple conflicting
objectives, as multi-objective optimization problem resorts to a number of
trade-off optimal solutions. Being a population based approach, GA are well
suited to solve multi-objective optimization problems. There are two
approaches to multi-objective optimization. One is a plain aggregating
approach where individual objective functions are combined into a single
composite function. The second approach is to determine an entire pareto-
optimal solution set (Konak et al 2006). A set of solutions is
said to be non-dominated set if no solution of the set is dominated by any
other solution. Non-dominated sorting is sorting of population according to
ascending level of non-domination. Pareto-optimal solution set is a set of
solutions that are non-dominated with respect to each objective. Pareto based
approach uses individual objectives to determine pareto-optimal solution set.
When moving from one pareto-solution to another, there is a certain amount
of sacrifice in one objective to achieve a certain amount of gain in the other.
Crowding distance is an estimate of the density of solutions surrounding a
particular solution in the population.
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In this chapter, two multi-objective optimization algorithms
Weighted Sum Genetic Algorithm (WSGA) and Elitist Non-dominated
sorting Genetic Algorithm (ENGA) are used. Redundancy is introduced in the
fault dropping phase of ENGA based ATPG. Two objectives, fault coverage
and power consumption are simultaneously optimized using these algorithms.
Experimental results are tabulated for ISCAS’85 combinational, enhanced
scan version of ISCAS’89 sequential circuits and ITC’99 benchmark circuits.
Results are obtained for four crossover operators namely one-point, two-
point, uniform and weight based crossover operators. The results obtained
demonstrate that the ENGA based ATPG with redundancy is effective in
providing a better fault coverage and minimum power dissipation for most of
the benchmark circuits.
5.2 WEIGHTED SUM GENETIC ALGORITHM
The weighted sum method is the most widely used classical
approach for handling multi-objective optimization problems. It combines a
set of objectives into a single objective by pre-multiplying each objective with
a user supplied weight. The weight of an objective is chosen in proportion to
the objective’s relative importance in the problem. Setting up an appropriate
weight also depends on the scaling of each objective function so that each
objective has more or less the same order of magnitude. After the objectives
are normalized, a composite objective function F(x) can be formed by
summing the weighted normalized objectives and thus the multi-objective
optimization problem is converted to a single-objective optimization problem
as given by Equation (5.1) (Zhao and Jiao 2006)
1
Maximize/Minimize F(x)M
m m
m
w f ( x ) (5.1)
wheremw is the weight of the m
th objective function and
mw value can be
between 0 to1.The sum of the weights should be equal to 1 as given in
Equation (5.2).
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1
1M
m
m
w (5.2)
The advantages of weighted sum approach are:
It is the simplest way to solve a multi-objective optimization
problem.
For problems having a complex pareto-optimal front, this
method guarantees finding solutions on the entire pareto-
optimal set.
5.3 WEIGHTED SUM GENETIC ALGORITHM FOR
CROSSTALK DELAY FAULT TESTING
The dual objectives used in WSGA are maximizing fault coverage
and minimizing power dissipation. In CMOS digital circuits it has been
proved that the parameter that affects the power and energy consumption is
the switching activity in the digital circuit.
5.3.1 Power Dissipation
In CMOS combinational circuits, power dissipation is due to the
following sources: i) Static power dissipation due to leakage currents and the
currents drawn continuously from the power supply. ii) Dynamic power
dissipation due to switching transient current and charging and discharging of
load capacitances (Weste and Eshraghian 2004). Unlike bipolar technologies,
where a majority of power dissipation is static, the bulk of power dissipation
in properly designed existing CMOS digital circuits is due to dynamic power
dissipation caused by charging and discharging of capacitances. Thus, a
majority of the low power design methodology is dedicated to reducing this
predominant factor of power dissipation. However, there are also other
components of power dissipation in CMOS circuits like short circuit current
power, leakage current power, and static biasing power. These are negligible
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when compared with the dynamic power dissipation. Denser designs, tighter
timing constraints, higher operating frequencies and lower applied voltages
affect the energy, average power, instantaneous power and peak power of a
silicon device during testing.
Consider a pseudo-random test sequence of length m, where m is
the test length required to achieve the targeted fault coverage, the total energy
consumed in the circuit during application of the complete test sequence is
given in Equation (5.3).
21/ 2 ( , )tot o DD wik iE C V S i k (5.3)
whereoC is the equivalent load capacitance, DDV is the power supply voltage
in CMOS logic, ),( kiS wi is the number of switching provoked by test vectors
Tk at node i, during the test time T.
The average power is the ratio between the total energy and the test
time as given in Equation (5.4).
totavg
EP
mT (5.4)
Instantaneous power is defined as the power consumed due to the application
of a synchronizing clock signal which will cause brown-out. It is given by the
Equation (5.5).
T
EP tk
inst (5.5)
wheretkE is the energy consumed in the circuit after application of a pair of
successive test vectors (Tk-1,Tk), i.e energy given in Equation (5.3) for a
particular pair of test vectors. The peak power consumption corresponds to
the highest switching activity generated in the CMOS digital circuit at any
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instant. The peak power consumption corresponds to the maximum of the
instantaneous power consumed during the test session. It is given by the
Equation (5.6).
T
EP tk
peak
)max( (5.6)
It is understood from the above expressions of the power and
energy consumption, for a given CMOS technology with specified supply
voltage of the circuit design, number of switchingwiS of node i is the
predominant factor that affects the power and energy consumption (Girard
2002). Hence the proposed work aims at reducing the switching activity in
digital CMOS circuits. Switching activity of digital circuits is the measure of
number of transitions at primary inputs and gate outputs. Hence the second
objective in WSGA based ATPG is minimizing the number of transitions.
5.3.2 WSGA Based Test Generation
The overall process of test generation using WSGA is shown in
Figure 5.1. An initial population is generated randomly containing individuals
of length 2Q, where Q is the number of primary inputs in each circuit. The
fitness of each individual are calculated using the fault simulator explained in
section 4 of chapter 4. The fitness function is given in
Equation (5.7).
1 2( * ) ( * )i rF w NF w NT (5.7)
whereiNF is the number of faults detected and rNT denotes the number of
transitions, the weights 1w = 0.6 and 2w =0.4. A pair of individuals is selected
based on the fitness values. Crossover operation is applied for the selected
pair of individuals to generate two new individuals with a crossover
probability of 1. For each bit value of the individuals generated, mutation
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operation is applied with a mutation probability of 0.1. Old individuals are
removed from the population and replaced with new individuals that have
optimal fitness value for the next generation. The algorithm is stopped when
the required number of generations is reached.
Figure 5.1 Flowchart of WSGA for Crosstalk Fault Testing
Selection
Crossover
No
Generate random initial population of
test sequences
Fitness evaluation using crosstalk
fault simulator
Mutation
Faults detected?
Yes
Start
No. of generations
reached?
Add the sequence
to test set & remove
the faults detected
End
No
Yes
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5.4 ELITIST NON-DOMINATED SORTING GENETIC
ALGORITHM
The difficulty with WSGA is in handling mixed optimization
problems, such as those with some objectives of the maximization type and
some of the minimization type, all objectives have to be converted into one
type. Further it is difficult to set the weight vectors to obtain a pareto-optimal
solution in a desired region in the objective space. Moreover different vectors
need not necessarily lead to different pareto-optimal solutions. They can lead
to an identical optimal solution. The computational complexity of the
weighted sum approach increases because more tests are needed to know
whether the obtained solution is truly a minimum solution. Further this
weighted sum approach cannot find certain pareto-optimal solutions in the
case of a non convex objective space.
Hence to have a diverse set of multiple non-dominated solutions
which converge close to the pareto-optimal front and with a good spread
multi-objective evolutionary algorithm, ENGA proposed by Deb (2002) is
used for solving multiple objectives. ENGA uses an elite preserving operator
and a diversity preserving mechanism. This diversity among non-dominated
solutions is introduced using the crowding distance operator which is used
with the tournament selection and during the population reduction phase. No
extra niching parameter is required as solutions compete with their crowding
distance. The elitism mechanism does not allow an already found pareto-
optimal solution to be deleted.
5.4.1 Elitism
Although the crossover and mutation are the core search operators
of GA, there exists a probability that the good solutions will not be carried
over to the next generation. Using elitism, it is possible to pass the best
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solutions of a particular generation to the next generation unaffected. This
helps the evolutionary algorithm to converge fast. Elitism is implemented by
merging the old and new population. The next generation is formed from this
combined population by selecting the best individuals, till the size of the new
population is same as the old one. Thus elite parents are allowed to compete
with their offspring for a slot in the next generation.
5.4.2 Pareto-Optimality and Concept of Domination
A set of solutions are said to be non-dominant if they are not
dominated by any other solution in the solution space. The set of all feasible
non-dominated solutions is referred to as the pareto-optimal set. For a given
pareto-optimal set, the corresponding objective function values in the
objective space are called the Pareto-optimal front.
5.4.3 ENGA Based Test Generation Algorithm
Elitist non-dominated sorting algorithm which uses a fast non-
dominated sorting procedure, an elitist-preserving approach, and a parameter
less niching operator (Deb et al 2002) is used for test generation of crosstalk
delay faults for solving multiple objectives. The flowchart for ENGA based
test generation algorithm is shown in Figure 5.2. A new random parent
population Pt is created with size N. The binary tournament selection,
recombination and mutation operators are used to create a child population Qt
of size N. A combined population Rt = Pt U Qt of size 2N is formed. A non-
dominated sorting as described in section 5.4.3.1 is used to classify the
population Rt.
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Figure 5.2 Overall Flow Process of ENGA for Crosstalk Fault Testing
End
Start
Generate parent population Pt
Select the mating pool
Crossover and mutation
Generate new children population Qt
Determine the fault coverage and number
of transitions
Perform the non-dominated sorting
to Rt
Perform crowding sort and obtain new
population
No. of
generations
reached?
No
Yes
Rt = Pt Qt
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Once the non-dominated sorting is over, the population Rt is filled
with solutions of different non-dominated fronts, first the best non-dominated
front, then with solutions of the second non-dominated front and so on. Since
the overall population size of Rd is 2N, all fronts may not be accommodated
in the new population of size N. So fronts which could not be accommodated
are simply deleted. When the last front is being considered, there exist more
solutions than the remaining slots in the new population. In that case,
members are chosen from the last allowed front using the crowding sort
method described in section 5.4.3.2. The next generation parent population
Pt+1 are filled by descending order of the crowding distance values. The next
generation offspring population Qt+1 is generated by crowding tournament
selection procedure and by crossover and mutation. The whole process is
continued till the required generations are reached.
5.4.3.1. Non-dominated sorting
The initialized population is sorted based on non-domination using
the following sorting algorithm.
Step 1: The first solution from the population is kept in an empty set P'.
Thereafter, each solution p (second solution onwards) is compared with all
members of the set P' one by one. If the solution p dominates any member of
P' then the solution p is removed from P'. If p is dominated by any member of
P', the solution p is ignored. If p is not dominated by any member of P', it is
included in P'. Once all members of population are checked the remaining
members of P' constitutes the non-dominated set. These are the best solutions
in a population. The pseudo code for filling a particular non-dominant front is
given in Figure 5.3.
Step 2: The entire population P is to be classified into various non-domination
levels. The pseudo code for non-dominated sorting of population is given in
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Figure 5.4. Initially all the non-dominated setsiF (i=1,2..) is set as empty
sets. The front counter is set as i=1. Using the procedure described in step 1
the non-dominated setiF of population P is found. Fi is deleted from P. The
counter is incremented and the steps are repeated until population set P is
empty.
Figure 5.3 Pseudo Code for Finding Non-Dominated Set
Figure 5.4 Pseudo code for Non-Dominated Sorting of Population
At the end of the operation, solutions of the first non-dominated front are
stored in F1 and solutions of the second non-dominated front are stored in F2
and so on.
Create a non-dominated set P' /*Include first member in P'*/
}1{'P /*Take one solution at a time*/
for each P p P /*for each p that is in P and not in P'
}{'' pPP /*include p in P' temporarily*/
for each pqPq ^' /*For each q in P' and is not p */.
if ,qp then };'\{' qPP /*If p dominates a member of P, delete it*/
else if pq , then };'\{' pPP /*If p is dominated by other members of
P do not include p in P*/
F= Fast non dominated sort (P);
;1i /* Initialize the front counter*/
UntilP /* until the population set is not
empty */
iF = Find non dominated front (P);
iFPP / ; /* Non-dominated front is removed
from P*/.
1ii ; /*Increment counter*/
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5.4.3.2 Crowding strategy
Crowding distance calculation is the determination of Euclidean
distance between individuals in a front based on their ‘m’ objectives in the m-
dimensional space. All the individuals in the population are assigned a
crowding distance value, as the individuals are selected based on rank and
crowding distance.
Step1: Let the number of non-dominated fronts be denoted as n= |f|. For each
solution k in the set assign crowding distance dk=0.
Step2: For each objective function m=1, 2,..M (Number of Objectives), sort
the individuals based on objective m , Im = sort (fm, m).
Step3: Assign to the boundary solutions infinite value i.e., dI1m = dIn
m = ,
Step4: Assign for the solutions j=2 to n-1, the crowding distance value as
given by Equation (5.8)
+ (5.8)
The index Ij denotes the solution index of the j-th member in the sorted list.
The second on the right hand side of equation is the difference in objective
function values between two neighboring solutions on either side of solution
Ij. The parameter max
mf and min
mf are set as population-maximum and
population-minimum values of the mth
objective function.
5.4.4 ENGA Based ATPG
The ENGA based ATPG consists of two phases. In the first phase
the initial population of test sequences is generated based on a pseudo random
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process. If a sequence detects a fault, that sequence is added to the set, which
is given as input to the second phase. In the second phase child population is
created from population obtained in the first phase, by using selection,
crossover and mutation operators. To the combined parent and child
population ENGA procedure described in section 5.4.3 is applied to obtain the
new population. The faults that are detected are removed from the fault list
and the test sequence is added to the test set. The remaining faults are passed
to the next sequence.
The fitness functions used in ENGA based ATPG is given by
Equations (5.9) and (5.10)
1 i iF NF FC (5.9)
2 rF NT (5.10)
where iNF is the number of faults that is given to the ith test sequence, iFC is
the number of faults covered by that test sequence and rNT is the number of
transitions during the application of the i-th test sequence.
5.4.5 ENGA Based ATPG with Redundancy
In ENGA based ATPG a redundancy is introduced in test
generation process. The aim in introducing redundancy is to allow ENGA to
select better test sequences so as to minimize the number of transitions during
test pattern generation. Redundancy is introduced by modifying the fault
dropping phase, where a fault is dropped only if it is covered by at least M
sequences, where M being the redundancy factor.
The pseudo code of the overall algorithm is given in Figure 5.5.
The overall algorithm is same as ENGA based ATPG except that the faults
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detected by final population are only removed from the fault list. The phase I
and phase II of the algorithm is repeated for maximum number of runs
denoted as maxruns. The pseudo code of phase I of ENGA based ATPG
algorithm with redundancy is shown in Figure 5.6.
Figure 5.5 Pseudo code of Overall ENGA Based ATPG
In this phase the pseudo random sequences are fault simulated for the faults in
the fault list. If the sequence detects fault, that fault is removed from the fault
list only after it is detected by M sequences and the corresponding sequence is
added into the solution set. If no faults are detected by the sequence, then the
last sequence generated in the corresponding cycle is added to the set. This
process is repeated for maximum iterations denoted as Max_iter. The pseudo
code for phase II is shown in Figure 5.7. From the parent
population obtained in the phase I, the child population is obtained using the
selection, crossover and mutation. The new population is obtained by
applying ENGA procedure described in section 5.4.3. For each generation the
fault list is forwarded and redundancy fault dropping approach is used. The
Overrall algorithm
{
FL= {reduced set of crosstalk delay faults}
for(i=0;i<maxruns,i++)
{
initial pop=phase I (FL);
if (FL =NULL)
break;
phase II (initial pop, FL);
Faults detected only by end population are
removed from the fault list.
}
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faults that are detected only by the end population are removed from the fault
list.
Figure 5.6 Pseudo Code of Pseudorandom Generation of Initial Test
Sequence
Once the population is evolved for a given number of generations, the
population obtained at this stage is evaluated. If a sequence in that population
detects a fault, that fault is dropped from the fault list and that sequence is
added to test set. Number of transitions calculated for that sequence is
considered in the evaluation of power dissipation for the circuit under test.
The length of the test sequence is twice the number of primary inputs.
Number of generations is denoted as no_gen and population size is denoted as
popsize.
Function Phase I
initial pop(FL)
For (i=0; i<Max_iter, i++)
{
initial pop=phase I(FL);
randomly generate sequences of length L;
for (each sequence)
{if sequence detects faults in the fault list
{
add sequence to the test set;
drop the faults detected only if they are detected by M sequences;
}
}
return (initial population);
}
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Figure 5.7 Pseudo Code of Final Test Generation
5.5 EXPERIMENTAL RESULTS
In this section the results for test generation using Weighted Sum
Genetic Algorithm, Elitist Non-dominated sorting Genetic Algorithm and
Elitist Non-dominated sorting Genetic Algorithm with redundancy are
presented. Tests are generated for most of the ISCAS’85 combinational
circuits, several enhanced scan version of ISCAS’89 sequential circuits and
Function Phase II
{
Initial pop from phase1;
for (l=0;l<no_gen;l++)
{
for (k=0; k<popsize;k++)
{
obtain new population by applying selection, crossover and mutation
operators;
}
for (each sequence in the new population)
if (sequence detects the faults in the fault list
{ add sequence to the solution set;
drop the faults detected only if they are detected by M sequences
sequence;
}
FL which is given to ENGA phase is forwarded from one generation to
next generation without any modification.
}
}
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ITC’99 benchmark circuits. The WSGA based test generator and ENGA
based test generator is implemented in INTEL core I7 processor with 2.6 GHz
and 4GB RAM using C language in Linux environment.
WSGA based ATPG, ENGA based ATPG and ENGA based ATPG
with redundancy is run for the four crossover operators namely one-point
crossover, two-point crossover, uniform crossover and weight based
crossover. During test generation, the number of generations is varied as 4, 8,
12 and 16. For large benchmark circuits more number of generations is
chosen to get better results. Choice of the number of generations and
population size is a tradeoff between fault coverage, execution time and
number of transitions. A population size of 4, 8, 12 and 16 is used. The
maximum number of iterations in phase 1 is limited to 5.The maximum
number of runs denoted as maxruns is limited to 3. A crossover probability of
1 and mutation probability of 0.1 is used. The selection scheme used is the
binary tournament selection. Redundancy factor is selected carefully because
both the test generation time and reduction in number of transitions depend on
this. By experimental trial, redundancy factor of 5 is chosen. Unit delay
crosstalk delay fault simulator is used to evaluate the fitness function.
Experiments are performed using WSGA based test generation.
Table 5.1 and Table 5.2 depict the number of faults detected and number of
transitions for all the crossover schemes respectively. The bold number
represents the maximum faults detected and minimum number of transitions
for each circuit respectively. The number of faults detected using weight
based crossover is greater than that of the other crossover schemes for 17 of
24 benchmark circuits. The minimum number of transitions for weight based
crossover is obtained for 6 of the 24 benchmark circuits. CPU time is nearly
equal for all the crossovers.
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Table 5.1 Experimental Results for WSGA Based ATPG
CircuitNo. of Faults Detected
Uniform 1-Point 2-Point WCO
c17 42 42 41 41
c432 7955 7946 7970 7970
c880 8873 8873 8874 8885
c499 20658 20529 20666 20726
c1355 127670 126220 126675 126701
c1908 23998 23884 23223 24326
c3540 9787 9778 9870 9882
c7552 130981 134778 130034 132881
s27 66 65 68 66
s208 647 630 664 676
s208.1 472 528 454 530
s298 524 530 525 525
s344 1182 1185 1186 1184
s386 4121 4112 4047 4136
s420.1 1197 1151 1148 1197
s820 7636 7684 7538 7718
s510 1073 1082 1077 1095
s526 879 882 878 882
s953 2876 2822 2966 2877
s1196 10297 10138 10163 10398
s1238 4392 4514 4428 4614
s1423 15374 15289 15333 15380
s1488 4278 4280 4293 4299
s13207.1 195212 195201 195261 195245
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Table 5.2 Experimental Results for WSGA Based ATPG
CircuitNo. of Transitions
Uniform 1-Point 2-Point WCO
c17 363 369 386 360
c432 75860 77464 76425 78308
c880 136385 142222 141328 137715
c499 108632 107962 108422 108800
c1355 293023 295590 297221 296609
c1908 484799 489909 492100 484691
c3540 856214 857121 858908 859012
c7552 2077961 2089081 2081300 2076670
s27 664 663 630 663
s208 32203 32095 32154 32207
s208.1 30689 31086 31097 31253
s298 14129 13460 13852 14092
s344 53016 53019 50272 52130
s386 38698 39109 39456 38675
s420.1 58496 59368 58588 58483
s820 75410 76109 75242 75621
s510 58249 55498 57002 58257
s526 53809 54294 53622 55799
s953 83328 83328 83328 83328
s1196 91379 90665 91198 90536
s1238 58897 58208 58083 59386
s1423 181431 182007 181009 181402
s1488 155551 160142 143068 157125
s13207.1 3758980 3762214 3755541 3750233
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Table 5.3 and Table 5.4 represent the number of faults detected and
number of transitions for each circuit for ENGA based ATPG for all the
crossover schemes. It is observed that two point crossover gives better fault
coverage for larger benchmark circuits than other crossover schemes. The
number of faults detected using two-point crossover is greater than that of the
other crossover schemes for 15 of 24 benchmark circuits. The number of
transitions for two-point crossover is minimum for 5 of 24 benchmark
circuits. The CPU time in seconds is the execution time of ENGA based
ATPG for two point crossover.
Experimental results for ENGA based ATPG with redundancy is
summarized in Table 5.5 and Table 5.6. From experimental results it is
observed that two-point crossover gives better fault coverage for 14 of 24
benchmarks. The number of transitions is minimum for two-point crossover
for 3 of 24 benchmark circuits.
Table 5.7 shows the number of faults detected and number of
transitions for ENGA based ATPG with redundancy for ITC’99 Benchmark
circuits. The results are observed for two-point crossover.
Table 5.8 summarizes the results for ENGA based ATPG with
redundancy using unit delay simulator and rise/fall delay simulator. The
number of faults detected, number of transitions, number of test vectors and
CPU time are compared. Results are obtained using two-point crossover. The
fault coverage decreases for ENGA based ATPG using rise/fall delay fault
simulator and hence number of transitions is also less compared to ENGA
based ATPG using unit delay simulator. The CPU time in seconds gives the
execution time of the ENGA based test generation. The CPU time for ENGA
based ATPG using unit delay simulator is less compared to ENGA based
ATPG using rise/fall delay fault simulator.
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Table 5.9 shows percentage increase in fault coverage and
percentage reductions in transitions for ENGA based ATPG and ENGA based
ATPG with redundancy over WSGA based ATPG. Results are tabulated for
two-point crossover.
Table 5.3 Experimental Results for ENGA Based ATPG
CircuitNo. of Faults Detected
Uniform 1-Point 2-Point WCO
c17 38 38 38 38
c432 7951 7958 7958 7960
c880 8654 8649 8613 8685
c499 20689 20722 20723 20708
c1355 130071 130290 130870 130492
c1908 22559 22610 22667 22579
c3540 9884 9801 9912 9901
c7552 133194 132998 133318 130299
s27 70 70 70 70
s208 608 650 708 670
s208.1 500 493 493 509
s298 525 522 525 524
s344 1182 1185 1182 1182
s386 4160 4142 4115 4101
s420.1 1076 1001 999 1016
s820 7637 7580 7692 7650
s510 1073 1070 1073 1081
s526 881 881 881 881
s953 2824 2874 2999 2868
s1196 9479 9518 9608 9606
s1238 4134 4162 4170 4167
s1423 15411 15346 15415 15373
s1488 3980 4084 4202 4060
s13207.1 196839 196630 196910 196872
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Table 5.4 Experimental Results for ENGA Based ATPG
CircuitNo. of Transitions CPU Time(s)
Uniform 1-Point 2-Point WCO
c17 252 243 242 253 0.013
c432 64590 67806 67553 68675 27.5
c880 125087 126624 126450 127934 9.4
c499 94511 95561 95091 95533 11.4
c1355 264103 264745 265652 265409 388.2
c1908 434799 435690 433188 435299 296.4
c3540 776723 776970 779980 777331 682.7
c7552 1837961 1836390 1868900 1839088 965.2
s27 419 399 401 393 0.015
s208 25137 25839 26049 26013 0.35
s208.1 23572 23761 23626 23797 0.36
s298 12355 12535 12644 12749 0.23
s344 43731 43850 44988 43047 0.98
s386 33207 34326 33586 34273 2
s420.1 48407 48487 48323 50023 1.3
s820 64435 65900 79149 66641 4.8
s510 47495 48813 49855 48982 0.64
s526 49332 48727 47883 48648 1.26
s953 69440 69440 69440 69440 2.9
s1196 68824 67426 69146 68648 7.2
s1238 41951 42071 42379 42033 8
s1423 145967 146251 148460 148113 30.8
s1488 114879 117420 117041 114537 3.9
s13207.1 3236970 3237611 3236402 3236581 2766.7
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Table 5.5 Experimental Results for ENGA Based ATPG with
Redundancy
CircuitNo. of Faults Detected
Uniform 1-Point 2-Point WCO
c17 42 41 41 41
c432 8585 8585 8589 8588
c880 8650 8619 8640 8718
c499 20529 20585 20590 20570
c1355 128539 128401 128609 128522
c1908 24081 24440 24392 24221
c3540 9920 9923 9931 9926
c7552 133096 133220 133431 133303
s27 70 72 72 70
s208 713 663 680 652
s208.1 523 558 515 522
s298 525 528 518 526
s344 1186 1189 1187 1187
s386 4152 4153 4161 4159
s420.1 1112 1042 1080 1077
s820 7711 7717 7700 7700
s510 1092 1092 1090 1087
s526 879 883 885 884
s953 2824 2976 2990 2835
s1196 9754 9676 9688 9751
s1238 4585 4174 4094 4110
s1423 15380 15323 15414 15390
s1488 4238 4232 4261 4231
s13207.1 196885 197001 197389 196302
114
Table 5.6 Experimental Results for ENGA Based ATPG with
Redundancy
CircuitNo. of Transitions
Uniform 1-Point 2-Point WCO
c17 217 178 206 176
c432 58644 58666 60387 62030
c880 108900 112951 112489 112848
c499 87282 89094 88945 87890
c1355 236176 236503 237242 236612
c1908 353844 354899 352765 354009
c3540 566111 566801 567120 566248
c7552 1641854 1642843 1642982 1641795
s27 287 285 325 279
s208 22792 23009 23183 23379
s208.1 20912 20655 21025 21046
s298 9408 9471 9420 9650
s344 38435 39516 39738 41308
s386 29288 29982 29476 30609
s420.1 44223 44412 44463 44602
s820 58896 58941 58626 59549
s510 43431 44353 46216 45702
s526 43480 44063 43990 43634
s953 62496 62496 62496 62496
s1196 62829 62311 62065 60875
s1238 36539 36023 35663 36337
s1423 134068 126614 132165 129293
s1488 95067 94541 98884 98089
s13207.1 2668874 2650021 2655410 2641387
115
Table 5.7 Experimental Results for ENGA Based ATPG with
Redundancy for ITC’99 Benchmark Circuits
Circuit No. of Faults
Detected
No. of Transitions CPU Time(s)
b01_C 313 599 0.067
b02_C 87 347 0.017
b03_C 2790 5533 1.58
b04_C 10339 28109 302.7
b06_C 454 17174 0.233
b08_C 2452 14213 1.95
b10_C 1265 16245 0.917
b11_C 3670 61125 47.9
b14_C 284941 2931817 11095.3
b20_C 1095709 11218268 43112.5
b22_C 372657 11239573 38231.7
11
6
Table 5.8 Results for ENGA Based ATPG with Redundancy using Unit delay and Rise/Fall delay Simulator
Circuit
Unit Delay Rise/Fall Delay
No. of Faults
Detected
No. of
Transitions
No. of Test
Vectors
CPU Time
(s)
No. of Faults
Detected
No. of
Transitions
No. of Test
Vectors
CPU Time
(s)
c17 41 206 30 0.017 32 236 32 0.33
c880 8640 112489 384 13.2 6717 97688 384 30.85
c499 20590 88945 544 10.3 8283 41714 512 21.16
c1355 128609 237242 544 410.21 74538 91220 512 456.02
c1908 24392 352765 544 330.5 3696 156636 512 360.9
c3540 9931 567120 544 760.2 3723 389300 512 800.54
c7552 133431 1642982 544 1089.5 57641 1166517 512 1327.2
s27 72 325 30 0.017 63 279 32 0.33
s208 680 23183 256 0.417 624 22698 384 1.56
s208.1 515 21025 320 0.43 433 20188 320 1.53
s298 518 9420 128 0.27 485 8529 128 0.583
s344 1187 39738 320 1.18 720 15163 320 1.41
s386 4161 29476 320 1.9 3853 25404 320 4.7
s420.1 1080 44463 320 1.3 1043 42404 320 4.68
s820 7700 58626 320 5.35 7377 55725 320 21.6
s510 1090 46216 320 0.86 1039 39704 320 1.4
s526 885 43990 320 0.88 763 40723 320 4.5
s953 2990 62496 160 3.3 1562 30187 160 5.067
s1196 9688 62065 192 7.4 7535 32097 192 13.5
s1238 4094 35663 128 8.3 2168 22880 128 11.15
s1423 15414 132165 320 33.4 12901 98546 320 64.1
s1488 4261 98884 256 4.2 3360 68637 256 9.16
s13207.1 197389 2655410 544 3316.1 91808 2289146 512 3568.2
117
The bold number represents the maximum number of faults detected
and minimum number of transitions obtained for each circuit. It can be observed
that with a slight decrease (0.77%) in the fault coverage, ENGA based ATPG
achieves a good reduction in transition activity (17.76%). When redundancy is
introduced in ENGA based ATPG, results observed showed a slight increase in
fault coverage (0.7%) with a high degree of reduction in transition activity
(27.96%). Redundancy is introduced by modifying the fault dropping phase,
where a fault is dropped only if it is covered by 5 sequences. The number of test
vectors that detected faults and CPU time is slightly greater when redundancy is
introduced compared with ENGA based ATPG without redundancy.
Table 5.10 shows percentage increase in fault coverage and
percentage reductions in transitions for ENGA based ATPG and ENGA based
ATPG with redundancy over WSGA for larger benchmark circuits. The bold
number represents the maximum number of faults detected and minimum
number of transitions obtained for each circuit. It is observed that with a slight
increase in the fault coverage (0.78%), ENGA based ATPG achieves a good
reduction in transition activity (12.46%). When redundancy is introduced in
ENGA based ATPG, results observed showed an increase in fault coverage
(1.88%) with a high degree of reduction in transition activity (26.51%). The
experimental results indicate that ENGA based ATPG with redundancy gives
better fault coverage with minimum number of transitions for all the benchmark
circuits.
Figure 5.8 show the comparison between the execution time of ENGA
based ATPG and WSGA based ATPG. The execution time of WSGA based
ATPG is higher for all the benchmark circuits compared to ENGA based ATPG.
11
8
Table 5.9 Comparison of Fault Coverage and Number of Transitions
Circuit
WSGA Based ATPG ENGA Based ATPG ENGA Based ATPG with redundancy
FaultCoverage
(%)
No. ofTransitions
Fault Coverage(%)
No. ofTransitions
Decrease inFault
Coverage (%)
Decrease inTransitions
(%)
Fault Coverage(%)
No. ofTransitions
Increase inFault
Coverage(%)
Decrease inTransitions
(%)
c17 97.61 386 90.47 242 7.14 37.3 97.61 206 0 46.63
c432 85.45 76425 85.32 67553 0.13 11.6 92.08 60387 6.63 20.98
c880 95.63 141328 92.82 126450 2.81 10.52 93.11 112489 -2.52 20.41
c449 94.45 108422 94.71 95091 -0.26 9.43 94.10 88945 -0.35 17.96
s27 91.89 630 94.59 401 -2.7 36.34 97.29 325 5.4 48.41
s208 89.36 32154 95.28 26049 -4.3 18.18 91.52 23183 2.16 27.9
s208.1 81.36 31097 88.35 23626 -6.99 24.02 92.29 21025 10.93 32.38
s298 97.76 13852 97.76 12644 0 8.72 96.46 9420 -1.3 31.99
s344 99.66 50272 99.32 44988 0.34 10.51 99.74 39738 0.08 20.95
s386 96.47 39456 98.09 33586 -1.62 14.87 99.18 29476 2.71 25.29
s420.1 89.96 58588 78.29 48323 11.67 17.52 84.63 44463 -5.33 24.1
s820 97.41 75242 99.4 79149 -1.99 8.09 99.50 58626 2.09 22.08
s510 98.08 57002 97.72 49855 0.36 12.53 99.27 46216 1.19 18.92
s526 98.54 53622 98.87 47883 -0.18 10.7 99.32 43990 0.78 19.96
s953 97.69 83328 98.78 69440 -1.09 16.66 98.48 62496 0.79 25
s1196 95.6 91198 90.38 69146 5.22 27.05 91.13 62065 -3.93 31.94
s1238 76.05 58083 71.62 42379 4.43 27.03 70.31 35663 -5.74 38.59
s1423 98.96 181009 99.49 148460 -0.53 18.16 99.49 132165 0.53 26.98
s1488 99.72 143068 97.61 117041 2.11 18.19 98.98 98884 -0.82 30.88
Average 0.77 17.76 0.704 27.96
11
9
Table 5.10 Comparison of Fault coverage and Number of Transitions for Larger Benchmarks
Circuit
WSGA Based ATPG ENGA Based ATPG ENGA Based ATPG with redundancy
Fault
Coverage
(%)
No. of
Transitions
Fault
Coverage
(%)
No. of
Transitions
Increase in
Fault Coverage
over WSGA
(%)
Decrease in
Transitions over
WSGA
(%)
Fault
Coverage
(%)
No. of
Transitions
Increase in
Fault Coverage
over WSGA
(%)
Decrease in
Transitions over
WSGA
(%)
c1355 80.48 297221 83.15 264103 2.67 11.14 81.71 237242 1.23 20.17
c1908 89.60 492100 87.46 434799 -2.19 11.64 94.11 353844 4.31 28.09
c3540 87.71 858908 88.09 776723 0.38 14.02 88.25 567120 0.53 33.97
c7552 93.76 2081300 96.13 1837961 2.37 11.69 96.21 1642982 2.45 21.05
s13207.1 80.77 3755541 81.45 3236402 0.68 13.82 81.65 2655410 0.88 29.29
Average 0.78 12.46 1.88 26.51
120
Figure 5.8 Comparison of Execution Time
5.6 SUMMARY
In this chapter multi-objective evolutionary algorithms Weighted
Sum Genetic Algorithm and Elitist Non-dominated Sorting Genetic
Algorithm are used for testing crosstalk delay faults in VLSI circuits.
Redundancy is introduced in the fault dropping phase of ENGA based ATPG
and results are analyzed. Experimental results for ISCAS’85 combinational
and ISCAS’89 enhanced scan version of sequential circuits are presented.
ENGA based ATPG with redundancy increases the fault coverage with
reduced switching activity. The experimental results demonstrate the
effectiveness of the proposed approach. The method achieves 81% to 97%
fault coverage on combinational circuits and 70% to 99% fault coverage on
enhanced scan version of sequential circuits with an average of 27% reduction
in the number of transitions on combinational and enhanced scan version of
sequential circuits. Compared to WSGA based ATPG, ENGA based ATPG
with redundancy reduces the number of transitions with a slight increase in
fault coverage for most of the benchmark circuits.
0
5
10
15
20
25
30
35
40
45
c17
c432
c499
c880
s27
s208
s208.1
s298
s344
s386
s420.1
s820
s510
s526
s953
s1196
s1238
s1423
s1488
Execution Time of Benchmark Circuits
ENGA
WSGA
Benchmark Circuits
Exec
uti
on
Tim
e(s)