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Chapter 4 Memory Test Architectures and Techniques
1
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Chapter 4 Memory Test Architectures and Techniques
Figure 4-1 Introduction to Memory Testing
Logic Embedded
JTAG Boundary Scan
PLL TAP
Chip-Level
Memory
Memory Access
Chapter 4 Memory Test Architectures and Techniques
2
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-2 Memory Types
6 Transistor SRAM Cell
Column/Bit-DataColumn/Bit-Data
Row/Word-Address
Column/Bit-Data
Row/Word-Address
1 Transistor DRAM Cell
Column/Bit-Data
Row/Word-Address
2 Transistor EEPROM Cell
Storage Select
SelectStorage
Select Select
Storage
Chapter 4 Memory Test Architectures and Techniques
3
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-3 Simple Memory Organization
Memory: Data Width by Address Depth
32 x 512
Data In
Address In
Read/WriteBar
Output Enable
Data Out
Data Bus: To Multiple Memory Arrays
Address Bus: To Multiple Memory Arrays
Memory Array
Address Decode to Row Drivers
Data Decode to Column Drivers
Control Circuitry to Read, Write,and Data Output Enable
Control Signals: Individual Signals to This Memory Array
BusEnable
Chapter 4 Memory Test Architectures and Techniques
4
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-4 Memory Design Concerns
Chip FloorPlan
Memory 1
Memory2
Memory
3
Memory 4
- Aspect Ratio
- Access Time
- Power Dissipation
Chapter 4 Memory Test Architectures and Techniques
5
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-5 Memory Integration Concerns
Chip FloorPlan
Memory 1
Memory2
Memory
3
Memory 4
- Routing
- Placement & Distribution
- Overall Power Dissipation
Processor
LocalLogic
Chapter 4 Memory Test Architectures and Techniques
6
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-6 Embedded Memory Test Methods
EmbeddedMicroprocessor
Core
EmbeddedMemory
Array
EmbeddedMemory
Array
BIST Controller
EmbeddedMemory
Array
32
24
3
32
24
3
Functional Memory Test
Direct Access Memory Test
BIST Memory Test
Data
Control
Address
Data
Address
Control
Invoke
Reset
Hold
Done
Fail
Chapter 4 Memory Test Architectures and Techniques
7
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
row # —> 0
column # —>
row # —> 1
row # —> 2
0 1 2 3
data bit cell
Figure 4-7 Simple Memory Model
0 1
00
00
1
11
11
1
Chapter 4 Memory Test Architectures and Techniques
8
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
0 1 1
1 0 1 0
single bit stuck-at 1word stuck-at
single bit stuck-at 0
data value 1110
address A031—>
address A032—>
address A033—>
Figure 4-8 Bit-Cell and Array Stuck-At Faults
1 1 1 0
1
Data in Bit Cells
May Be Stuck-At
Logic 1 or Logic 0
Chapter 4 Memory Test Architectures and Techniques
9
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
horizontal (row)
word bridging
bit bridging
vertical (column)bit bridging
unidirectionalone-way short
word bridgingbidirectional
two-way short
randombit bridging
Figure 4-9 Array Bridging Faults
1
1
10 0
1 0 1 0
1 0
0 0 11
1 1 00
1
0 0 11
1 1 00
Data in Bit Cells
May Be Bridged
to Other Bit Cells
Chapter 4 Memory Test Architectures and Techniques
10
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
1 10 1
1 0 1 1
0 1 11
0 0 11
R
O
W
XX
X
Select Lines
Column Decode
R
o
w
D
e
c
o
d
e
Row Decode
stuck-at faults result
in always choosing
wrong address
Row Decode
bridging faults result
in always selecting
multiple addresses
Figure 4-10 Decode Faults
Column Decode
stuck-at faults result
in always choosing
wrong data bit
Column Decode
bridging faults result
in always selecting
multiple data bits
X
XX 1 1 11
11 11
Select Line
faults result in
similar array
fault effects
C
O
L
Chapter 4 Memory Test Architectures and Techniques
11
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Data around target
cell is written with
complement data
0 11 0
0 1 0 1
0 1 10
Figure 4-11 Data Retention Faults
01 01
Address 21 = A
Address 22 = 5
Address 24 = 5
alternating 5’s and A’s make for a natural checkerboard pattern
Address 23 = A
ComplementaryData aroundTarget Cell
Chapter 4 Memory Test Architectures and Techniques
12
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-12 Memory Bit Mapping
Physical Memory Organization
Physical Memory Organization
Physical Memory Organization
Logical Memory Organization
Blue: Pass
Red: Fail
ColumnData Fault
Row AddressFault
Stuck-AtBit Faults
BridgedCell Faults
Chapter 4 Memory Test Architectures and Techniques
13
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-13 Algorithmic Test Generation
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
1 0 1 0 1 0 1 0
1 0 1 0 1 0 1 0
1 0 1 0 1 0 1 0
1 0 1 0 1 0 1 0
1 0 1 0 1 0 1 0
1 1 1 0 1 0 1 0
Address 00 —>
Address 01 —>
Address 02 —>
Address 03 —>
Address 04 —>
Address 05 —>
Address 06 —>
Address 07 —>
Address 08 —>
Address 09 —>
Address 10 —>
Address 11 —>
Address 12 —>
Address 13 —>
Address 14 —>
Address 15 —>
Address 16 —>
Address 17 —>
Address 18 —>
Address 19 —>
Address 20 —>
Address 21 —>
Address 22 —>
Address 23 —>
Addr(00) to Addr(Max)Read(5)-Write(A)-Read(A)Increment Address
Addr(00) to Addr(Max)Read(A)-Write(5)-Read(5)Increment Address
Addr(Max) to Addr(00)Read(5)-Write(A)-Read(A)Decrement Address
Addr(Max) to Addr(00)Read(A)-Write(5)-Read(5)Decrement Address
Addr(Max) to Addr(00)Read(5)Decrement Address
Addr(00) to Addr(Max)Write(5)-InitializeIncrement Address
Read (A)
Increment Address
Write (5)Read (5)
------->
Memory Array with 24 Addresseswith Algorithm at Read (A) Stage
March C+ Algorithm
Chapter 4 Memory Test Architectures and Techniques
14
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
scan-memoryboundary
Detection ofincoming
Control ofoutgoingsignalssignals
Memory
Array
Figure 4-14 Scan Boundaries
Boundary at some levelof scanned registrationor “pipelining” away
from the memoryarray
Data
Address
Control
Data
Minimum RequirementDetection up to Memory Inputand Control of Memory Output
Concern: the Logic betweenthe Scan Test Area and theMemory Test Area Is notAdequately Covered
Non-Scanned Registration inside the Boundarybut Before the Memory Test Area Results in
a Non-Overlap Zone
Chapter 4 Memory Test Architectures and Techniques
15
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-15 Memory Modeling
Data In
Address
Data Out
Memory
Array
ATPG
Model
Control
Din
Ain
Read/Write
Dout
ScanArchitecture
The Memory Array is modeledfor the ATPG Engine so the
ATPG Tool can use the memoryto observe the inputs
and control the outputs
Chapter 4 Memory Test Architectures and Techniques
16
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
scan black-boxboundary
Detection ofincoming
Control ofoutgoingsignals
signals
Figure 4-16 Black Box Boundaries
Boundary at some levelis blocked off
as if the memory wascut out of the circuit
Observe-only registersused for detection of memory
input signals
Gate or Multiplexor is usedto Block—fix to a known
value—the Memory Output Signals
Address
Data In
Control
Scan Mode
Gated Data Out
Memory
Array
can be
removed
from
netlist for
ATPG purposes
Multiplexed Data Out
All Registersare in thescan chain
architecture
Chapter 4 Memory Test Architectures and Techniques
17
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
scan black-boxboundary
Detection ofincoming
Input is passedto output as theform of output
signals
Figure 4-17 Memory Transparency
Boundary at some levelis blocked off
as if the memory wascut out of the circuit
Observe-only registersused for detection of memory
input signals
Multiplexor is used topass the input directly
to the output
Address
Control
Memory
array
can be
removed
from
netlist for
ATPG purposes
Bypass Data OutData In
control
Chapter 4 Memory Test Architectures and Techniques
18
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-18 The Fake Word Technique
scan black-boxboundary
Detection of incomingdata signals done here
Input is passedto output with
registration
Boundary at some levelis blocked off
as if the memory wascut out of the circuit
Observe-only registersnot needed on data since
register emulates memory
Register and multiplexoris used to emulate memory
timing and output
Address
Control
Memory
array
can be
removed
from
netlist for
ATPG purposes
Bypass Data OutData In
In ideal sense,timing should
also be matched
Chapter 4 Memory Test Architectures and Techniques
19
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-19 Memory Test Needs
Memory: data width by address depth
32 x 512
Data In
Address
Read/WriteB
Output Enable
Data Out
Data Bus: Possibly to Multiple Memory Arrays
Address Bus: Possibly to Multiple Memory Arrays
Memory Array
Address Decode to Row Drivers
Data Decode to Column Drivers
Control Circuitry to Read, Write,and Data Output Enable
Control Signals: Individual Signals to This Memory Array
Test Must Access the Data, Address, and Control Signalsin order to Test This Memory
Chapter 4 Memory Test Architectures and Techniques
20
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-20 Memory BIST Requirements
Algorithm Controller
Address Generator
Data Generator
Comparator
Retention
Debug
Invoke Done
Fail
Debug_data
Invoke: Start BISTRetention: Pause BIST and Memory ClockingDebug: Enable BIST Bitmap Output
Fail: A Memory Has Failed a BIST TestDone: Operation of BIST Is CompleteDebug_data: Debug Data Output
INPUTS
OUTPUTS
Memory Array(s)
Chip Level
Address: Ability to Apply Address SequencesData: Ability to Apply Different Data SequencesAlgorithm: Ability to Apply Algorithmic Control Sequences
OPERATIONS
Comparator: Ability to Verify Memory Data
Chapter 4 Memory Test Architectures and Techniques
21
Design-for-Test for Digital IC’s and Embedded Core Systems
Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-21 An Example Memory BIST
Din
Ain
Write_en
Retention
Release
Bitmap
Invoke done
Fail
Bitmap_out
Dout
Invoke: invoke the BIST (apply muxes and release reset)Retention: enable retention algorithm and pauseRelease: discontinue and release pauseBitmap: enable bitmap output on fail occurrence
Fail: sticky fail flag—dynamic under bitmapDone: operation of BIST is completeBitmap_out: fail data under bitmap
INPUTS
OUTPUTS
Read_en
Clk
Com
parator
MemoryArrayDI
A
WRB
Do
CEB
Algorithm Controller
Address Generator
Data Generator Hold_out
Hold_out: indication of pause
Chapter 4 Memory Test Architectures and Techniques 22
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-22 MBIST Integration Issues
Invoke: a global signal to invoke all BIST units
Reset: a global signal to hold all BIST units in reset
Bitmap: a global signal to put all BIST units in debug mode
Hold_#: individual hold signals to place memories in retentionor to select which memory is displayed during debug
done: all memory BISTs have completed
fail: any memory BIST has detected a fault or a failure
diag_out: the memory BIST not in hold mode will present debug data
Chip Level
Invoke
Reset
Bitmap
Hold_1
Hold_2
Hold_3
Hold_4 sos1
bitmap_out4
bitmap_out3
bitmap_out2
bitmap_out1
done1 fail1
done2 fail2
done3 fail3
done4 fail4
done 1-4fail 1-4
done fail diag_out
Memory Arraywith BIST
Memory Arraywith BIST
Memory Arraywith BIST
Memory Arraywith BIST
Chapter 4 Memory Test Architectures and Techniques 23
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-23 MBIST Default Values
Invoke: must be a logic 0 when BIST is not enabled
Reset: should be a logic 0 when BIST is not enabled
Bitmap: should be a logic 0 when BIST is not enabled
Hold_#: should be a logic 0 when BIST is not enabled
done: should not be connected to package output pin when BIST is not enabled
fail: should not be connected to package output pin when BIST is not enabled
diag_out: should not be connected to package output pin when BIST is not enabled
Invoke
Reset
Bitmap
Hold_1
Hold_2
Hold_3
Hold_4so
s1
bitmap_out4
bitmap_out3
bitmap_out2
bitmap_out1
done1 fail1
done2 fail2
done3 fail3
done4 fail4
done 1-4
fail 1-4
done fail diag_out
Memory Arraywith BIST
Memory Arraywith BIST
Memory Arraywith BIST
Memory Arraywith BIST
Chapter 4 Memory Test Architectures and Techniques 24
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-24 Banked Operation
Invoke: global signal invokes bank 1 BIST
Reset: global signal holds bank 1 BIST in reset
Bitmap: global signal that enables BIST debug
Hold_#: paired hold signals to place memories in retentionor to select which memory is displayed during debug
done: bank n memory BISTs have completed
fail: any memory BIST has detected a fault or a failure
diag_out: the memory BIST not in hold will present debug data
Invoke
Reset
Bitmap
Hold_1
Hold_2
Hold_n
sos1
diag_out
done
fail
donefaildiag_out
Memory
Arrays
with
Independent
MBISTs
invoke1-m1-n
1-n
done1-m
fail1-m
n
n
n
Bank 2
m
Memory
Arrays
with
Independent
MBISTs
Bank 1
m
mnn
1-m
scan_out1-n
debug
hold_l1
hold_l2
hold_1m
Chapter 4 Memory Test Architectures and Techniques 25
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-25 LFSR-Based Memory BIST
LFSR - MISR
CLK
Address
Data
Control
Memory Array
LFSR - PRPG
D Q
CLK
MBIST
Functional
Functional
Functional Data In
MBIST Data In
MBIST
D Q D Q
5A0F
D QD QD Q
Functional & MBIST Data Out Data Out
AlgorithmSequencer
Chapter 4 Memory Test Architectures and Techniques 26
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-26 Shift-Based Memory BIST
10101010101010
001011001110001111000011
10
1110
1010
Address
Data
Read/Write
Memory Array
The Address sequence can be shiftedboth forward and backward to provide
all addresses
The Data sequence can be shiftedacross the data lines, and can also
provide data for a comparator
The Control sequence can beshifted across the read-write
or output enable or othercontrol signals
010010
Chapter 4 Memory Test Architectures and Techniques 27
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-27 ROM BIST
MBIST
Functional Data Out
LFSR - MISR
CLK
D QD QD Q
Address
Read Control
Data Out
Read-Only Memory Array
MBIST
Functional
MBIST
Functional
Chapter 4 Memory Test Architectures and Techniques 28
Design-for-Test for Digital IC’s and Embedded Core Systems Alfred L. Crouch© 1999 Prentice Hall, All Rights Reserved
Figure 4-28 Memory Test Summary
Memory Testing Fundamentals Summary
Memory Testing Is Defect-Based
Memory Testing Is Algorithmic
Memory Testing Relies on Multiple-Clue Analysis
A Memory Test Architecture May CoExist with Scan
Modern Embedded Memory Test Is BIST-Based
BIST-Based Testing Allows Parallelism
Parallel Testing Impacts Retention Testing
Parallel Testing Impacts Power Requirements
BIST Is the Moving of the Tester into the Chip
A Memory Can Block Scan Test Goals
Different Types of Memories—Different Algorithms
A Memory Fault Model Is Wrong Data on Read
Parallel Testing Requires Chip-Level Integration