Post on 23-Feb-2021
CDA 4213/CIS 6930CDA 4213/CIS 6930
CMOS VLSI DesignCMOS VLSI Design
Lecture 11Lecture 11
Delay EstimationLinear Delay Model
Slide 2
Source: Prof. David Harris’ Slidesand Dr. Athan's lecture.
CMOS VLSI Design Slide 3
Outline Delay Definitions RC Delay Model Elmore Delay Model Delay Components Summary
CMOS VLSI Design Slide 4
Delay Definitions tpdr: rising propagation delay
– From input to rising output crossing VDD/2
tpdf: falling propagation delay
– From input to falling output crossing VDD/2
tpd: average propagation delay
– tpd = (tpdr + tpdf)/2
tr: rise time
– From output crossing 0.2 VDD to 0.8 VDD
tf: fall time
– From output crossing 0.8 VDD to 0.2 VDD
CMOS VLSI Design Slide 5
Delay Definitions tcdr: rising contamination delay
– From input to rising output crossing VDD/2
tcdf: falling contamination delay
– From input to falling output crossing VDD/2
tcd: average contamination delay
– tpd = (tcdr + tcdf)/2
CMOS VLSI Design Slide 6
Delay Definitions Rise/fall times are also called slopes and edge rates.
Propagation and contamination delay times are also called max-times and min-time, respectively.
The gate that charges or discharges a node is called the driver and the gates and wire being driven are called the load.
Propagation delay is usually the most relevant value of interest, and is often simply called delay.
A timing analyzer computes the arrival times at each node and checks that the outputs arrive by their required time.
Positive slack means that the circuit meets timing.
Negative slack means the circuit is not fast enough.
CMOS VLSI Design Slide 7
Simulated Inverter Delay Solving differential equations by hand is too hard SPICE simulator solves the equations numerically
– Uses more accurate I-V models too! But simulations take time to write
(V)
0.0
0.5
1.0
1.5
2.0
t(s)0.0 200p 400p 600p 800p 1n
tpdf = 66ps tpdr = 83psVin Vout
CMOS VLSI Design Slide 8
Delay Estimation We would like to be able to easily estimate delay
– Not as accurate as simulation– But easier to ask “What if?”
The step response usually looks like a 1st order RC response with a decaying exponential.
Use RC delay models to estimate delay– C = total capacitance on output node– Use effective resistance R– So that tpd = RC
Characterize transistors by finding their effective R– Depends on average current as gate switches
CMOS VLSI Design Slide 9
Delay Estimation
From p. 144.
CMOS VLSI Design Slide 10
Delay Estimation
CMOS VLSI Design Slide 11
RC Delay Models Treats a transistor as a switch in series with a resistor
where the effective resistance is the ratio of Vds to Ids averaged across the switching interval of interest.
Effective Resistance values (R) are based on approximations - Process driven: Where will you find this information during the layout and verification steps
Gate and Diffusion Capacitance – Although capacitances have a non-linear voltage dependence, we use a single average value. From Section 2.3.1, we roughly estimate C for a minimum length transistor to be 1fF/μm of width. In a 65nm process with a unit transistor being 0.1μm wide, C is about 0.1fF.
CMOS VLSI Design Slide 12
RC Delay Models Calculating or estimating parasitics in integrated circuits
is one of the most complex steps in the design/layout (fabrication) process. Notice I said “design” and “layout”, implying these terms are interconnected.
The level of complexity is proportional to operating frequency (why?). So are salaries (why?).
Not just onchip but the wires, bumps, pads, pins, probes, sockets, wires, etc.
It becomes black magic at >GHz frequencies and often solved exclusively by magicians and wizards.
The implication here is that the best IC engineers are really “analog” design engineers, whether you like it or not.
Name some of the top analog design engineers.
CMOS VLSI Design Slide 13
RC Delay Models
CMOS VLSI Design Slide 14
RC Delay Models Use equivalent circuits for MOS transistors
– Ideal switch + capacitance and ON resistance– Unit nMOS has resistance R, capacitance C– Unit pMOS has resistance 2R, capacitance C
Capacitance proportional to width Resistance inversely proportional to width
kg
s
d
g
s
d
kCkC
kCR/k
kg
s
d
g
s
d
kC
kC
kC
2R/k
CMOS VLSI Design Slide 15
Example: 3-input NAND Sketch a 3-input NAND with transistor widths chosen
to achieve effective rise and fall resistances equal to a unit inverter (R). (Example4.2)
3
3
222
3
CMOS VLSI Design Slide 16
3-input NAND Caps Annotate the 3-input NAND gate with gate and
diffusion capacitance.
2 2 2
3
3
3
CMOS VLSI Design Slide 17
3-input NAND Caps Annotate the 3-input NAND gate with gate and
diffusion capacitance.
2 2 2
3
3
33C
3C
3C
3C
2C
2C
2C
2C
2C
2C
3C
3C
3C
2C 2C 2C
CMOS VLSI Design Slide 18
3-input NAND Caps Annotate the 3-input NAND gate with gate and
diffusion capacitance.
9C
3C
3C3
3
3
222
5C
5C
5C
CMOS VLSI Design Slide 19
Transient Response 4.3.4 Transient Response Calculation Follow through the process of solving a 1st- and 2nd-
order (system) equation (Figures 4.8 and 4.10).
CMOS VLSI Design Slide 20
Example: 3-input NAND Sketch a 3-input NAND with transistor widths chosen
to achieve effective rise and fall resistances equal to a unit inverter (R).
CMOS VLSI Design Slide 21
Elmore Delay ON transistors look like resistors Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder
R1 R2 R3 RN
C1 C2 C3 CN
( ) ( )nodes
1 1 1 2 2 1 2... ...
pd i to source ii
N N
t R C
RC R R C R R R C
- -»
= + + + + + + +
å
CMOS VLSI Design Slide 22
Elmore Delay
CMOS VLSI Design Slide 23
Elmore Delay
CMOS VLSI Design Slide 24
Example: 2-input NAND Estimate rising and falling propagation delays of a 2-
input NAND driving h identical gates.
h copies6C
2C2
2
22
4hC
B
Ax
Y
CMOS VLSI Design Slide 25
Example: 2-input NAND Estimate rising and falling propagation delays of a 2-
input NAND driving h identical gates.
h copies6C
2C2
2
22
4hC
B
Ax
Y
R
(6+4h)CY ( )6 4pdrt h RC= +
CMOS VLSI Design Slide 26
Example: 2-input NAND Estimate rising and falling propagation delays of a 2-
input NAND driving h identical gates.
h copies6C
2C2
2
22
4hC
B
Ax
Y
( ) ( ) ( ) ( )( )
2 2 22 6 4
7 4
R R Rpdft C h C
h RC
= + + +é ùë û= +
(6+4h)C2CR/2
R/2x Y
CMOS VLSI Design Slide 27
Delay Components Delay has two parts
– Parasitic delay• 6 or 7 RC• Independent of load
– Effort delay
• 4h RC
• Proportional to load capacitance
CMOS VLSI Design Slide 28
Contamination Delay Best-case (contamination) delay can be substantially
less than propagation delay. Ex: If both inputs fall simultaneously
6C
2C2
2
22
4hC
B
Ax
Y
R
(6+4h)CYR
( )3 2cdrt h RC= +
CMOS VLSI Design Slide 29
7C
3C
3C3
3
3
222
3C
2C2C
3C3C
IsolatedContactedDiffusionMerged
UncontactedDiffusion
SharedContactedDiffusion
Diffusion Capacitance we assumed contacted diffusion on every s / d. Good layout minimizes diffusion area Ex: NAND3 layout shares one diffusion contact
– Reduces output capacitance by 2C
– Merged uncontacted diffusion might help too
CMOS VLSI Design Slide 30
Layout Comparison Which layout is better?
AVDD
GND
B
Y
AVDD
GND
B
Y
CMOS VLSI Design
Summary Lumped RC delay model
– Estimates delay by computing lumped R and lumped C
– Limitation – Overestimates the delay Elmore Delay Model
– Distributed delay estimation
Slide 31
CMOS VLSI Design
End Lecture
Q&A