Post on 15-May-2015
CAMBRIA NETWORK COMPUTER
Operating Manual
For GW2350 Network Processor
Document #10000554
Revision 02 15 September 2008
Copyright 2008
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TABLE OF CONTENTS
TABLE OF CONTENTS ............................................................................................................................. 2
1. INTRODUCTION............................................................................................................................... 4
1.1. Product Description .................................................................................................................... 4
1.2. Standard Features ....................................................................................................................... 4
1.3. Ordering Options – Standard Configuration* ............................................................................ 4
1.4. Functional Blocks ........................................................................................................................ 5 Processor ............................................................................................................................................... 6 SDRAM DDRII .................................................................................................................................... 6 Flash ...................................................................................................................................................... 6 Mini-PCI ............................................................................................................................................... 7 Ethernet ................................................................................................................................................. 7 Host USB .............................................................................................................................................. 7 Serial EEPROM .................................................................................................................................... 7 Temperature and Voltage Monitor ........................................................................................................ 8 Watchdog Timer ................................................................................................................................... 8 Serial I/O ............................................................................................................................................... 8 Digital I/O ............................................................................................................................................. 9 JTAG Programming Port ...................................................................................................................... 9 Status LEDs .......................................................................................................................................... 9 Primary DC/DC Converter.................................................................................................................... 9 Optional GPS .......................................................................................................................................10 Optional RS485 Serial Port ..................................................................................................................11
2. CONFIGURATION AND INSTALLATION ..................................................................................12
2.1. Memory Mapping .......................................................................................................................12
2.2. PCI Device Mapping ..................................................................................................................13
2.3. Interrupt Mapping ......................................................................................................................13
2.4. Digital I/O Mapping ...................................................................................................................14
2.5. Interface Connectors ..................................................................................................................15 JTAG Port Header (J1) ........................................................................................................................16 Optional GPS MMCX Connector (J2) .................................................................................................16 Optional GPS UFL Connector (J3) ......................................................................................................16 Mini-PCI Socket (J4) ...........................................................................................................................16 Auxiliary Input Power Connector (J5) .................................................................................................18 Optional RS485 Serial Port Connector (J6) .........................................................................................18 Front Panel Ethernet Connectors (J7, J8) .............................................................................................18 Front Panel Dual USB Host Connector (J9) ........................................................................................19 Application Header (J10) .....................................................................................................................19
3. SOFTWARE .......................................................................................................................................20
3.1. Getting Started ...........................................................................................................................20
3.2. Board Support Package ..............................................................................................................20 Host USB .............................................................................................................................................20 Serial EEPROM ...................................................................................................................................20
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Temperature and Voltage Monitor .......................................................................................................21 Serial Ports ...........................................................................................................................................21 Status LED ...........................................................................................................................................21 Digital I/O ............................................................................................................................................22 Watchdog Timer ..................................................................................................................................23 Optional GPS .......................................................................................................................................23 Optional RS485 ....................................................................................................................................23
3.3. JTAG Programming ...................................................................................................................23 GW11008 USB JTAG Programmer with Linux ..................................................................................23 GW11008 USB JTAG Programmer with Windows ............................................................................24 GW11008 USB Serial Console with Linux or Windows .....................................................................24
3.4. Manufactures Website Links / Support Mailing List ..................................................................25 Hardware ..............................................................................................................................................25 Software ...............................................................................................................................................25
4. SPECIFICATIONS............................................................................................................................26
4.1. Electrical ....................................................................................................................................26
4.2. Environmental ............................................................................................................................26
4.3. Mechanical .................................................................................................................................26
5. CUSTOMER SUPPORT ...................................................................................................................28
5.1. Product Revision History ...........................................................................................................28
5.2. Technical Assistance ..................................................................................................................28
5.3. Warranty .....................................................................................................................................28
5.4. Return for Repair........................................................................................................................29
5.5. Life Support Policy .....................................................................................................................29
5.6. Copyright & Trademarks ...........................................................................................................29
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1. INTRODUCTION
1.1. Product Description The GW2350 is a member of the Gateworks Cambria Network Processor family.
This network processor consists of an Intel IXP435 XScale operating at 667MHz, 128Mbytes of DDRII-400 SDRAM, and 32Mbytes of Flash. Peripherals include a Type III Mini-PCI socket, two 10/100 Base-TX Ethernet ports with IEC-6100-4 ESD and EFT protection, and two USB Host ports. Additional features include serial EEPROM, watchdog timer, digital I/O, and system monitor to track operating temperature and input voltage. The GW2350 also supports digital I/O, GPS and RS485 serial as ordering options. Power is applied through either Ethernet connector with the unused signal pairs in a passive power over Ethernet architecture or through an auxiliary latching connector. An RS232 serial port is available through the JTAG connector using a Gateworks GW16027 JTAG Serial Port Adapter or a Gateworks GW11008 USB JTAG Programmer. A board support package is included for Linux 2.6 operating systems.
1.2. Standard Features Intel XScale IXP435 667MHz Processor
128Mbytes DDRII SDRAM Memory
32Mbytes Flash Memory
One Type III Mini-PCI Socket
Two 10/100 Ethernet Ports
Two v2.0 Host USB Ports
Digital I/O Control and Monitoring
1Kbyte Serial EEPROM
Voltage and Temperature Monitor
IXP Processor Watchdog Timer
JTAG Programming and Serial Console Port
Passive Power Over Ethernet
Reverse Voltage and Transient Protection
8 to 48VDC Input Voltage Range
8W Mini-PCI Socket Power
5W Typical Operating Power
Thermal Dissipation Rails
-40C to 85C Operating Temperature
Linux v2.6 Board Support Package
1 Year Warranty
Optional GPS and RS485 Serial Port
1.3. Ordering Options – Standard Configuration* Order Code IXP processor SDRAM Flash Mini-PCI Operating Temp
GW2350 IXP435 @ 667MHz 128Mbytes 32Mbytes 1 -40C to 85C * Contact factory for different configurations of CPU, DRAM, Flash, and support peripherals
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1.4. Functional Blocks The functional block diagram for the GW2350 network processor is shown below followed by a detailed description of each major functional block.
JTAG
ETHERNET
10/100 PHY
OPTIONAL GPS
OPTIONAL RS485
DDRII-400 SDRAM
64-128MBYTES
(128M STANDARD)
SYSTEM FLASH
8-32MBYTES
(32MB STANDARD)
ETHERNET
10/100 PHY
PROCESSOR
IXP435@
667MHZDC/DC SUPPLY
8-48VDC@15W
SERIAL EEPROM
SYSTEM MONITOR
WATCHDOG TIMER
MINI-PCI
(TOP)
DUAL HOST USB
DIO
PWR
Functional Block Diagram
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Processor
The Intel Xscale network processor line includes the IXP430, IXP432, and IXP435 processors. The features common to these processors are listed below. The primary differences between these processors are operating speed, support for hardware encryption, operating temperature and cost. The table below lists the differences between the processor families. The factory default GW2350 includes the extended temperature IXP435 processor operating at 667MHz.
StrongARM Version 5TE Compliant
Network processing engines to offload common Layer 2 functions
32-bit SDRAM DDRII interface operating at 400MHz
32-bit PCI interface operating at 33MHz for Mini-PCI support
16-bit Expansion interface for Flash and peripheral support
Two 802.3 MII/RMII interfaces for Ethernet PHY support
Two USB v2.0 host controllers support low, full, and high speed operation
16550 compliant serial port with 64-byte transmit and receive FIFOs
Internal bus performance monitoring unit
General purpose digital input/outputs
Spread spectrum clock support for reduced emissions
Feature IXP430 IXP432 IXP435
Speed (MHz) 400, 533, 667 400 400, 533, 667
Hardware Encryption No Yes Yes
Extended Temperature Option No Option
Cost Low Mid High
Processor Feature Comparison
SDRAM DDRII The DRAM resides in two synchronous DDRII-400 devices soldered directly to the board. This architecture supports DDRII memory capacities of 64Mbytes or 128Mbytes. The 32-bit DDRII interface operates at 400MHz. The factory default GW2350 includes 128Mbytes of DDRII-400.
Flash
The Flash resides in a single Intel StrataFlash device soldered directly to the board. This architecture supports Flash memory capacities from 8Mbytes up to 64Mbytes. The Flash is mapped into the IXP processor expansion bus address space. The factory default GW2350 includes 32Mbytes of Flash.
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Mini-PCI Mini-PCI is a small form factor PCI card that uses the same signal protocol, electrical specifications, and configuration definitions as conventional PCI. The GW2350 includes one Mini-PCI sockets on the top side of the board. The GW2350 increases the Mini-PCI specified maximum power rating from 2.5W per socket to 8W to meet the more demanding requirements of high power radios. The Mini-PCI sockets also support a low-ripple 5V supply capable of providing up to 8W of power to the Mini-PCI sockets. The additional power and low-ripple 5V supplies are ideal for present and future generations WiMAX cards. The mini-PCI socket is oriented to support cards 80mm, or longer. The mini-PCI site also includes sideband signaling for USB and digital I/O. These added signals support custom mini-PCI cards for adding functionality such as GSM telecommunications support.
Ethernet The GW2350 supports two Ethernet ports using National DP83848 physical layer transceivers. The Ethernet ports operate in a 100BASE-TX or 10BASE-T configuration and support auto MDI/MDIX for automatically switching receive and transmit pairs. Additional features include full-duplex operation for both 10Mbps and 100Mbps configurations as well as support for auto-negotiation. The data interface includes transient protection to IEC61000-4-2-ESD and IEC61000-4-4-EFT. The Ethernet ports are available through standard RJ45 connectors. The connectors have two integrated status lights. The green status light indicates link and activity. The green light is on for link and blinking for activity. The yellow status light indicates speed. The yellow light is on for 100Mbps and off for 10Mbps. Both connectors support passive power over Ethernet using the spare pins for input power and ground connections.
Host USB The GW2350 supports two v2.0 host USB ports directly from the IXP processor. The USB ports are Enhanced Host Controller Interface (EHCI) and USB Transceiver 2.0 Macrocell Interface (UTMI+) Level 2 compliant. The ports support all three standard data transfer rates of low speed (1.5Mbps), full speed (12Mbps), and high speed (480Mbps). The power switch for both ports includes over current protection, thermal protection, in-rush current limiting, and hot-plug noise filters.
Serial EEPROM The Atmel AT24C08 is an Electrically Erasable Programmable Read Only Memory (EEPROM) with 8Kbits of storage. The 8kbits of storage is organized in a 1048 x 8-bit configuration. Additional features include 1,000,000 erase/write cycles and a 100-year minimum data retention time. Data is transmitted between the EEPROM and the IXP processor using the I2C bus. The I2C clock frequency is 0 to 400 KHz. The I2C address for writes is A0 hex and for reads is A1 hex.
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Temperature and Voltage Monitor The Analog Devices AD7418 provides system monitoring of both operating
temperature and input voltage. The temperature accuracy is 1C at 25C and
2C over the entire temperature range of -40C to +125C. The input voltage is scaled down so that the data must be multiplied by 23.1 to get the actual voltage. Data is transmitted between the System Monitor and the IXP processor using the I2C bus. The I2C clock frequency is 0 to 400 KHz. The I2C address for writes is 50 hex for and for reads is 51 hex.
Watchdog Timer The GW2350 implements the IXP processor watchdog timer using digital I/O 12 as an enable. The IXP processor supports the watchdog timer with several registers for unlocking access, enabling timer, monitoring status, and setting time period. The steps listed below are required for updating the watchdog timer. These steps are performed automatically by Linux if the built-in driver is used.
Disable interrupts
Unlock watchdog access
Update watchdog timer
Lock watchdog access
Enable interrupts
Serial I/O The IXP processor includes a single asynchronous serial port. This serial port is connected to the JTAG programming connector in a digital configuration as shown in the following figure. The serial port is 16550-compliant with 64-byte transmit and receive buffers and supports transfer rates from 1.2Kbps up to 120Kbps. The GW2350 also supports a Texas Instruments TL16C752B dual UART to interface to the optional GPS and RS485 serial port. The UART is 16550-compliant with 64-byte transmit and receive buffers. The UART is mapped to the IXP processor expansion bus. The lower serial port interfaces to the optional GPS and interrupts the IXP processor with an active high signal on digital I/O 3. The upper serial port interfaces to the optional RS485 connector and interrupts the IXP processor with an active high signal on digital I/O 4.
PROCESSOR
IXP435@
667MHZ EXPANSION
UART
JTAG
RS485
TRANSCEIVER
GPS
CONTROLLERTTYS1
TTYS2
EXPB
TTYS0
Serial I/O Architecture
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Digital I/O The GW2350 supports digital I/O from the IXP processor for controlling and monitoring various local peripheral devices as well as an optional digital I/O expansion header for interfacing to external peripherals. The local devices include watchdog timer strobe and status LED as well as interrupts from the mini-PCI expansion socket, optional RS485 serial port, optional GPS serial port, and optional GPS pulse per second.
JTAG Programming Port The primary purpose of the JTAG Port is for automated factory testing and to facilitate program download into Flash memory. This feature requires the GW11008 USB JTAG Programmer. The JTAG programming port also includes the IXP processor asynchronous serial port in a logic-level configuration. This feature requires the GW11008 or the GW16027 JTAG Serial Adapter to convert the 3.3V serial port signals to standard RS232 levels. Instructions on using the Gateworks JTAG Programmer are given in Section 2 of this manual.
Status LEDs There are three surface mount status LEDs located near the rear panel edge of the GW2350. Two of the LEDs display the presence of 3.3V and 5.0V power. The third LED is software programmable using digital I/O 8 of the IXP processor. The hardware power up state for the software programmable LED is off.
Primary DC/DC Converter A switching DC to DC converter supplies power to the GW2350. This allows support for a wide input voltage range and higher power radios with efficiencies as high as 95% depending on operating voltage and load current.
Feature Benefit
High efficiency (up to 95%) Reduces heat generated in enclosure
Wide range (8-48VDC) Operates in wide variety of applications
High power (up to 30W) Supports high power mini-PCI cards
Thermal shutdown Protects against over heating
Output current limit Protects against short circuits
Controlled startup Reduces component stress and power surges
Reverse voltage protection Protects against improper installation
Transient protection Protects against input voltage spikes
Common mode input filter Reduces emissions for agency certification
Primary DC/ DC Converter Features
The input power is supplied through an auxiliary latching connector or through either RJ45 Ethernet connector in a passive power over Ethernet configuration on the unused data pairs. The voltage drop due to the resistance of the Ethernet cable between the GW2350 and the power injector must be considered when selecting the power supply operating voltage. The following guidelines should be considered when powering the board:
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If using an 802.3af supply, the device signature should be disabled and the deliverable power set to maximum. The passive PoE architecture does not return a device signature.
If using a passive PoE supply or injector, ensure that it is rated for the necessary voltage and power.
The connectors are both diode protected so that powering through one will not back feed through the other.
The positive input voltage must be applied to pins 4 and 5 of the RJ45 cable.
The negative input voltage must be applied to pins 7 and 8 of the RJ45 cable.
The RJ45 connector is rated for a 1.5A maximum current. It may be necessary to increase the operating voltage to lower the current depending on the total power required.
The RJ45 connector is not a hot plug connector and ALL CABLE CONNECTIONS SHOULD BE MADE BEFORE POWER IS APPLIED.
The GW2350 is classified at a Safety Extra Low Voltage Device (SELV) since the maximum input voltage is below the 60VDC SELV limit as defined by IEC 60950-1 and other standards.
Optional GPS The optional Trimble Copernicus module delivers complete position, velocity, and time information. The module supports Trimble Standard Interface Protocol (TSIP), Trimble ASCII Interface Protocol (TAIP), and National Marine Electronics Association (NMEA) protocols at a 1Hz update rate. A UFL connector is provided for an externally mounted active antenna. The GPS communicates to the IXP processor though the lower serial port of a dual UART mapped to the IXP processor expansion bus. The pulse-per-second signal is mapped to digital I/O 2 of the IXP processor to support either an interrupt or polled architecture. The primary features are listed below. The GPS is available as a special ordering option.
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Key Parameter Specification
Tracking Sensitivity -160 dBm
Acquisition Sensitivity (High Sensitivity Mode) -148 dBm
Acquisition Sensitivity (Std Sensitivity Mode) -142 dBm
Hot Start 3 seconds
Warm Start 35 seconds
Cold Start 38 seconds
Re-acquisition 2 seconds
Horizontal Accuracy @ 50% <2.5m
Horizontal with SBAS Accuracy @ 50% <2.0m
Altitude Accuracy @ 50% <5.0m
Altitude with SBAS Accuracy @ 50% <3.0m
Velocity 0.06m/s
PPS (Static) +/-100ns rms
PPS (Stationary Mode @ -145dBM) +/-350ns rms
GPS Parameters
Optional RS485 Serial Port An optional RS485 serial port is available in a half-duplex configuration through a 2-pin connector. The serial port interface includes protection against electrostatic discharge and electrical fast transients for operation in harsh environments. Failsafe termination prevents spurious interrupts when no driving source is connected. Thermal shutdown protects against excessive power dissipation caused by extended bus contention or a direct short. Exceptionally low input impedance supports up to 50 similar transceivers on a single bus. The maximum data rate is 115Kbaud with the standard 1.8432MHz oscillator. Data rates up to 3Mbps are possible by replacing the standard oscillator. The RS485 serial port is implemented using the upper serial port of a dual UART mapped to the IXP processor expansion bus. The RS485 serial port is available as a special ordering option.
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2. CONFIGURATION AND INSTALLATION The following section gives memory, interrupt, I2C and digital I/O mappings specific to the GW2350. See the Intel IXP3X Product Line of Network Processors Developer’s Manual for more information on these interfaces.
2.1. Memory Mapping The memory map and Expansion bus chip select mapping is shown below.
Memory Address Size Description
0000_0000 – 0FFF_FFFF 256Mbyte Flash Memory During Boot
0000_0000 – 3FFF_FFFF 1Gbyte SDRAM DDRII Memory
4000_0000 – 47FF_FFFF Reserved
4800_0000 – 4FFF_FFFF 128Mbyte PCI Data
5000_0000 – 53EF_FFFF 63Mbyte Flash Memory After Boot
53E0_0000 – 53E3_FFFF 256Kbyte Compact Flash Socket Select 0
53E4_0000 – 53E7_FFFF 256Kbyte Compact Flash Socket Select 1
53E8_0000 – 53F3_0000 768Kbyte Reserved for Future Expansion
53F4_0000 – 53F7_FFFF 256Kbyte Octal Status LED Latch
53F8_0000 – 53FB_FFFF 256Kbyte Optional RS485 Serial Port
53FC_0000 – 53FF_FFFF 256Kbyte Optional GPS Serial Port
5400_0000 – 5FFF_FFFF Reserved
6000_0000 – 63FF_FFFF 64Mbyte Queue Manager
6400_0000 – BFFF_FFFF Reserved
C000_0000 – C3FF_FFFF 64Mbyte PCI Controller Configuration and Status
C400_0000 – C7FF_FFFF 64Mbyte Expansion Bus Configuration
C800_0000 – C800_0FFF 4Kbyte High Speed UART
C800_1000 – C800_1FFF Reserved
C800_2000 – C800_2FFF 4Kbyte Performance Monitor
C800_3000 – C800_3FFF 4Kbyte Interrupt Controller
C800_4000 – C800_4FFF 4Kbyte GPIO Controller
C800_5000 – C800_5FFF 4Kbyte Timers
C800_6000 – C800_6FFF 4Kbyte Network Processor A
C800_7000 – C800_7FFF Reserved
C800_8000 – C800_8FFF 4Kbyte Network Processor C
C800_9000 – C800_9FFF Reserved
C800_A000 – C800_AFFF 4Kbyte Ethernet MAC on NPE C
C800_B000 – C800_BFFF Reserved
C800_C000 – C800_CFFF 4Kbyte Ethernet MAC on NPE A
C800_D000 – CC00_E4FF Reserved
CC00_E500 – CC00_F5FF 4.25Kbyte DDRII Configuration Registers
CC00_F600 – CCFF_FFFF Reserved
CD00_C000 – CDFF_FFFF 16Mbyte USB Host Controller 1
CE00_C000 – CEFF_FFFF 16Mbyte USB Host Controller 2
CF00_0000 – FFFF_FFFF Reserved
Note: The Flash is remapped by Redboot using bit 31 of the EXP_CONFG0 register.
Memory Map
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Chip Select Description
CS0 and CS1 System Flash Memory
CS2 Optional GPS Expansion UART
CS3 Optional RS485 Expansion UART
Expansion Bus Chip Selects
2.2. PCI Device Mapping The GW2350 PCI device mapping is listed below.
Bus Number
Device Number
Fcn Number
IRQ
Number
Description
00 01 0 28 Mini-PCI Slot
PCI Device Map
2.3. Interrupt Mapping The IXP processor allows for 32 interrupts which originate from either internal processor blocks or from the 14 dedicated digital I/O pins. The interrupt mapping is shown below.
Interrupt Function
0 Network Processor A
1 Reserved
2 Network Processor C
3 Queue Manager (1-32)
4 Queue Manager (33-64)
5 General Purpose Timer 0
6 DIO(0) – See discussion on digital I/O mapping
7 DIO(1) – See discussion on digital I/O mapping
8 PCI Interrupt
9 PCI DMA Channel 1
10 PCI DMA Channel 2
11 General Purpose Timer 1
12 Reserved
13 Reserved
14 Timestamp Timer
15 UART
16 Internal Watchdog Timer
17 Performance Monitoring Unit
18 Performance Monitoring Unit
19 DIO(2) – See discussion on digital I/O mapping
20 DIO(3) – See discussion on digital I/O mapping
21 DIO(4) – See discussion on digital I/O mapping
22 DIO(5) – See discussion on digital I/O mapping
23 DIO(6) – Peripheral I2C Bus SCL
24 DIO(7) – Peripheral I2C Bus SDA
25 DIO(8) – See discussion on digital I/O mapping
26 DIO(9) – See discussion on digital I/O mapping
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27 DIO(10) – Mini-PCI INTB 28 DIO(11) – Mini-PCI INTA 29 DIO(12) – See discussion on digital I/O mapping
30 Software Interrupt 0
31 Software Interrupt 1
Interrupt Map
2.4. Digital I/O Mapping The GW2350 supports digital I/O from the IXP processor for controlling and monitoring various local peripheral devices as well as an optional digital I/O expansion header for interfacing to external peripherals. The IXP processor includes three 16-bit registers for configuring, initializing, and controlling the digital I/O. The output enable register (GPOER) configures each bit as an input or output. The data output register (GPOUTR) controls the digital I/O configured as outputs. The input register (GPINR) reads the digital I/O configured as inputs. The IXP processor digital I/O mapping is shown below.
DIO Direction Default Description Optional Description 0 In Digital I/O Header Pin 3 None
1 In USB Clock Source Digital I/O Header Pin 4
2 In Optional GPS PPS Digital I/O Header Pin 5
3 In Optional GPS Interrupt Digital I/O Header Pin 6
4 In Optional RS485 Interrupt Digital I/O Header Pin 7
5 Out Software Status LED Digital I/O Header Pin 8
6 Out I2C Bus SCL None
7 Bi I2C Bus SDA None
8 In Digital I/O Header Pin 9 None
9 In Digital I/O Header Pin 10 None
10 In Mini-PCI Interrupt B None
11 In Mini-PCI Interrupt A None
12 In Watchdog Timer Enable Digital I/O Header Pin 11
13 Out PCI Reset None
14 Out PCI Clock None
15 Out Expansion Bus Clock None
Digital I/O Map
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2.5. Interface Connectors The GW2350 interface connector pin assignments and signal descriptions are included in the following sections. The connectors are listed in the table below and the connector locations are shown in the following diagrams.
Connector Populated Function
J1 Yes JTAG Port Header
J2 No Optional GPS MMCX Connector
J3 No Optional GPS UFL Connector
J4 Yes Mini-PCI Socket
J5 No Auxiliary Input Power Connector
J6 No Optional RS485 Serial Port Connector
J7 Yes Ethernet 1 Connector with Passive PoE Support
J8 Yes Ethernet 2 Connector with Passive PoE Support
J9 Yes Optional Dual USB Host Connector
J10 Yes Optional Application Header
Connectors
JTAG/SERIAL (J1)
OPTIONAL GPS MMCX (J2)
OPTIONAL GPS UFL (J3)
MINIPCI (J4)
AUXILIARY
INPUT POWER (J5)
OPTIONAL
RS485 (J6)
ENET 1
(J7)
ENET 2
(J8)
USB
(J9)
OPTIONAL
APP (J10)
Top Side Component Locations
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JTAG Port Header (J1) The JTAG programming port is available through a 14-pin header in a 2x7 configuration with 0.1-inch pin spacing. The mating connector is an AMP/Tyco 1658622-2, available from Digi-Key as part number AKN14B-ND. The primary purpose for the JTAG Port is to facilitate program download into Flash memory. This feature requires the GW11008 USB JTAG Programmer. The JTAG programming port also includes a three-wire logic-level configuration of the IXP processor serial port. This feature requires ether the GW11008 or the GW16027 JTAG Serial Adapter to convert the 3.3V serial port signals to standard RS232 levels.
Pin Signal Pin Signal
1 3.3V 2 COM1 RXD (3.3V)
3 JTAG RST 4 Ground
5 JTAG TDI 6 Ground
7 JTAG TMS 8 Ground
9 JTAG TCK 10 Ground
11 JTAG TDO 12 Board Reset
13 COM1 TXD (3.3V) 14 Ground
JTAG Port Header
Optional GPS MMCX Connector (J2) The optional GPS feature includes an alternate antenna connector for an externally mounted active antenna. The MMCX antenna connector is a vertical mount Molex 73415-2061, or equivalent.
Optional GPS UFL Connector (J3) The optional GPS feature includes an antenna connector for an externally mounted active antenna. The UFL antenna connector is a vertical mount Sunridge MCBG-ST-00T, or equivalent.
Mini-PCI Socket (J4) The Type II Mini-PCI socket expands peripheral support with high-speed PCI devices. In addition to the standard signaling, the connector includes USB and digital I/O sideband signals. These sideband signals support custom mini-PCI boards for GSM telecommunications.
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Pin Signal Connect Pin Signal Connect Pin Signal Connect
1 TIP NC 44 AD26 AD26 87 AD7 AD7
2 RING NC 45 CBE3# CBE3# 88 VCC3 3.3V
3 LANRXP NC 46 AD24 AD24 89 VCC3 3.3V
4 LANTXP NC 47 AD23 AD23 90 AD6 AD6
5 LANRXN NC 48 IDSEL IDSEL 91 AD5 AD5
6 LANTXN NC 49 Ground Ground 92 AD4 AD4
7 LANRSV NC 50 Ground Ground 93 Reserved Reserved
8 LANRSV NC 51 AD21 AD21 94 AD2 AD2
9 LANRSV NC 52 AD22 AD22 95 AD3 AD3
10 LANRSV NC 53 AD19 AD19 96 AD0 AD0
11 LANGNP NC 54 AD20 AD20 97 VCC5 5.0V
12 LANRNN NC 55 Ground Ground 98 Reserved Reserved
13 LANYEP NC 56 PAR PAR 99 AD1 AD1
14 LANYEN NC 57 AD17 AD17 100 Reserved Reserved
15 CHSGND CHSGND 58 AD18 AD18 101 Ground Ground
16 Reserved Reserved 59 CBE2# CBE2# 102 Ground Ground
17 INTB# INTB# 60 AD16 AD16 103 ACSYNC NC
18 VCC5 5.0V 61 IRDY# IRDY# 104 M66EN NC
19 VCC3 3.3V 62 Ground Ground 105 ACDIN NC
20 INTA# INT# 63 VCC3 3.3V 106 ACDOUT NC
21 Reserved Reserved 64 FRAME# FRAME# 107 ACCLK NC
22 Reserved Reserved 65 CLKRUN# Pull Down 108 ACID0 NC
23 Ground Ground 66 TRDY# TRDY# 109 ACID1 NC
24 VCC3AX 3.3V 67 SERR# SERR# 110 ACRST NC
25 CLK CLK 68 STOP# STOP# 111 AMON NC
26 RST# RST# 69 Ground Ground 112 Reserved Reserved
27 Ground Ground 70 VCC3 3.3V 113 AGND NC
28 VCC3 3.3V 71 PERR# PERR# 114 Ground Ground
29 REQ# REQ# 72 DEVSEL# DEVSEL# 115 AOUT NC
30 GNT# GNT# 73 CBE1# CBE1# 116 AIN NC
31 VCC3 3.3V 74 Ground Ground 117 AGND GPIO2
32 Ground Ground 75 AD14 AD14 118 AINGND USB+
33 AD31 AD31 76 AD15 AD15 119 AGND GPIO1
34 PME# NC 77 Ground Ground 120 AGND USB-
35 AD29 AD29 78 AD13 AD13 121 Reserved Reserved
36 RSVD RSVD 79 AD12 AD12 122 MPCIACT NC
37 Ground Ground 80 AD11 AD11 123 VCC5AX 5.0V
38 AD30 AD30 81 AD10 AD10 124 VCC3AX 3.3V
39 AD27 AD27 82 Ground Ground 125 CHSGND CHSGND
40 VCC3 3.3V 83 Ground Ground 126 CHSGND CHSGND
41 AD25 AD25 84 AD9 AD9 127 NC NC
42 AD28 AD28 85 AD8 AD8 128 NC NC
43 Reserved Reserved 86 CBE0# CBE0#
Mini-PCI Sockets
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Auxiliary Input Power Connector (J5) The GW2350 can be powered through a 4-pin header in a 1x4 configuration with 2mm pin spacing. This architecture works well for applications where connecting input power through the Ethernet connectors is not desirable. The mating connector is a JST PAP-04V-S, available from Digi-Key as part number 455-1488-ND. The mating connector pins are JST SPHD-002T-P05, available from Digi-Key as part number 455-1313-1-ND.
Pin Signal Pin Signal
1 Vin+ 2 Vin+
3 Ground 4 Ground
Auxiliary Input Power Connector
Optional RS485 Serial Port Connector (J6) An optional half duplex RS485 serial port is available through a 2-pin header in a 1x2 configuration with 2mm spacing. The mating connector is a JST PAP-02V-S, available from Digi-Key as part number 455-1486-ND. The mating connector pins are JST SPHD-002T-P05, available from Digi-Key as part number 455-1313-1-ND.
Pin Signal Pin Signal
1 Data+ 2 Data-
Optional RS485 Connector
Front Panel Ethernet Connectors (J7, J8) Both of the GW2350 Ethernet ports are available through standard 8-pin RJ45 connectors. These connectors support passive power over Ethernet enabling the GW2350 to be powered over the unused connector pins. The input voltage requirements are given in the specifications section of this manual.
Pin Signal Standard Wire Color (T568A)
Standard Wire Color (T568B)
1 TX+ Green/White Orange/White
2 TX- Green Orange
3 RX+ Orange/White Green/White
4 PPoE V+ Blue Blue
5 PPoE V+ Blue/White Blue/White
6 RX- Orange Green
7 PPoE GND Brown/White Brown/White
8 PPoE GND Brown Brown
Ethernet Connectors
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Front Panel Dual USB Host Connector (J9) The GW2350 supports two Host USB ports through a standard dual stack Type A connector.
Pin Signal Cable Color
1 USB1 Switched 5V Red
2 USB1 Data- White
3 USB1 Data+ Green
4 Ground Black
5 USB2 Switched 5V Red
6 USB2 Data- White
7 USB2 Data+ Green
8 Ground Black
Dual USB Host Connector
Application Header (J10) The application header includes power, ground, digital I/O, and optically isolated digital I/O. This is a 20-pin header is a 2x10 configuration with 0.05-inch pin spacing. The mating connector must be purchased as a cable assembly from Samtec using part number FFSD-20-D-x.x-01-N, where x.x is the cable length specified in inches.
Pin Signal Pin Signal
1 Reserved 2 Reserved
3 DIO(0) 4 DIO(1)
5 DIO(2) 6 DIO(3)
7 DIO(4) 8 DIO(5)
9 DIO(12) 10 Ground
11 DIO(8) Opto Out 12 DIO(8) Opto Rtn
13 DIO(9) Opto Out 14 DIO(9) Opto Rtn
15 Vin+ 16 Ground
17 Vin+ 18 Ground
19 Vin+ 20 Ground
Optional Application Header
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3. SOFTWARE
3.1. Getting Started The GW2350 is factory configured with both Redboot and Linux programmed into Flash memory. The software is configured for terminal output through the JTAG serial port as a console. The JTAG serial port requires the GW16027 JTAG Serial Adapter or the GW11008 USB JTAG Programmer.
Remove power from the GW2350.
Connect the GW2350 serial console to a host computer running a terminal emulation program, such as Windows HyperTerminal.
Configure the terminal emulation program for 115200 baud, 8 data bits, 1 stop bit, no parity, and no flow control.
Apply power to the GW2350 using the passive power over Ethernet through either Ethernet connector.
Redboot and Linux output will appear on the serial console. It is also possible to communicate to the GW2350 using a telnet session over Ethernet.
Connect the GW2350 Ethernet port to a host computer with either a standard or a crossover cable.
The GW2350 default IP address is 192.168.1.1. Configure the Host Computer IP address to be on the same subnet, for example 192.168.1.99.
Switch to the Host Computer and type C:> telnet 192.168.1.1.
The GW2350 console information will be routed to the Host Computer display.
3.2. Board Support Package The Gateworks Linux BSP includes support for most standard and optional GW2350 peripherals.
Host USB The Host USB uses the Intel EHCI specification with added register support for embedded solutions. The standard EHCI drivers included in the vanilla 2.6.25 and later revision kernels work on the GW2350.
Serial EEPROM The serial EEPROM locations from 0x100 to 0x200 are reserved for Gateworks use only. Modifying these locations of the EEPROM will cause the board to become unstable.
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Temperature and Voltage Monitor Temperature and voltage data is accessed through the sysfs file system which is typically mounted at /sys. The following command reads the temperature:
# cat /sys/bus/i2c/devices/ 0-0028/temp1_input
The following command reads the voltage:
# cat /sys/bus/i2c/devices/ 0-0028/in1_input
Serial Ports The JTAG header serial port is included in the IXP43x processor so drivers are found in the vanilla kernel. The optional GPS and RS485 serial ports are included in the expansion bus UART. The drivers for the UART are included in the Gateworks BSP. These drivers provide access to the serial devices using /dev/ttyS0, /dev/ttyS1, and /dev/ttyS2.
Status LED The status LED is controlled through the sysfs file system. The status LEDs is listed as user in the /sys/class/leds directory. Change to the appropriate directory before sending the following commands to control the state of the LED. The following commands turn the led on.
# echo 1 > brightness
The following commands turn the led off.
# echo 0 > brightness The following command configures the led for load monitor operation.
# echo “heartbeat” > trigger The following command configures the led for timer operation. The delay value is expressed in milliseconds.
# echo “timer” > trigger # echo [value] > delay_on # echo [value] > delay_off
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Digital I/O The digital I/O utility contained in the Gateworks BSP is used to control the state of general purpose I/O. The associated bit value is listed in the table below. The driver masks the digital I/O bits that the user is permitted to modify. The following command sets a digital I/O bit to an input.
# gpioctl dirin [bit] The following command sets a digital I/O bit to an output.
# gpioctl dirout [bit] The following command sets a digital I/O bit to a logical zero.
# gpioctl clear [bit] The following command sets a digital I/O bit to a logical one.
# gpioctl set [bit] The following command reads the state of a digital I/O bit.
# gpioctl get [bit]
DIO Direction Default Description Optional Description 0 In Digital I/O Header Pin 3 None
1 In USB Clock Source Digital I/O Header Pin 4
2 In Optional GPS PPS Digital I/O Header Pin 5
3 In Optional GPS Interrupt Digital I/O Header Pin 6
4 In Optional RS485 Interrupt Digital I/O Header Pin 7
5 Out Software Status LED Digital I/O Header Pin 8
6 Out Reserved None
7 Bi Reserved None
8 In Digital I/O Header Pin 9 None
9 In Digital I/O Header Pin 10 None
10 In Reserved None
11 In Reserved None
12 In Watchdog Timer Enable Digital I/O Header Pin 11
13 Out Reserved None
14 Out Reserved None
15 Out Reserved None
Digital I/O Mapping
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Watchdog Timer The GW2350 implements the IXP processor watchdog timer using digital I/O 12 as an enable. The IXP processor supports the watchdog timer with several registers for unlocking access, enabling timer, monitoring status, and setting the time period. If the ixp4xx_wdt driver is compiled as a module, the following command sets the heartbeat timeout.
# modprobe ixp4xx_wdt heartbeat=[seconds] If the ixp4xx_wdt driver is compiled into the kernel, the heartbeat timeout is fixed at 60 seconds. The following command starts the watchdog timer and specifies the time between watchdog strobes.
# watchdog –t [seconds] /dev/watchdog
Optional GPS The GPS communicates with a standard NEMA 3.0 data stream using 4800, 8, n, 1 settings on serial port 1. The following commands can be used to display the GPS. See the Serial Port discussion for additional information.
# stty –F/dev/ttyS1 4800 # cat /dev/ttyS1
Optional RS485 See the Serial Port discussion for additional information.
3.3. JTAG Programming The GW2350 Flash memory is programmed through the JTAG port. Gateworks offers two JTAG programming solutions that enable a software developer to download application programs or to recover the factory default Flash image.
GW11008 USB JTAG Programmer when using a PC USB port with either Linux or Windows operating system.
GW16013 Gang Programmer for programming up to 16 GW2350 network processors in a production environment.
GW11008 USB JTAG Programmer with Linux a) Connect the GW11008 JTAG-USB Programmer to the JTAG header on
an Avila or Cambria network processor using the attached ribbon cable. b) Power on the Avila or Cambria network processor. c) Connect the GW11008 JTAG-USB Programmer to a PC USB port using
the supplied USB cable. d) Copy the Linux directory from the CDROM into a local directory on your
x86 Linux machine. The tool prerequisites include the LIBC library. e) Run the JTAG program with the syntax shown below.
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# ./jtag –p <filename> –u <filename> –v <filename>
Option Operation
-p Program Flash device using specified filename
-v Verify Flash device using specified filename
-u Upload Flash device using specified filename
Example 1: Program the Flash with SG06_16M.bin image.
# ./jtag -p SG06_16M.bin Example 2: Program and verify Flash with SG06_16M.bin image.
# ./jtag -p SG06_16M.bin -v SG06_16M.BIN
GW11008 USB JTAG Programmer with Windows a) Insert CD and follow installation steps to add programmer icon to
desktop. b) Connect the GW11008 JTAG-USB Programmer to the JTAG header on
an Avila or Cambria network processor using the attached ribbon cable. c) Power on the Avila or Cambria network processor. d) Connect the GW11008 JTAG-USB Programmer to a PC USB port using
the supplied USB cable. e) Double click on installed icon to open the application. f) Select any combination of program, verify, and upload. g) Select or specify the appropriate file names. BSP Images are installed by
default in the C:\images directory. h) Select go. It will take a minute to see any activity. Depending on the
image, a Program, Verify, or Upload operation can take up to ten minutes.
GW11008 USB Serial Console with Linux or Windows The JTAG connector on all Avila and Cambria network processors includes a serial port. To access the serial port, click on the JTAG-USB icon for Windows or type # ./jtag –w on the Linux command line to properly initialize the JTAG-USB programmer before launching the terminal emulation program.
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3.4. Manufactures Website Links / Support Mailing List The section provides links to hardware and software related web sites. An email mailing list is also available for Cambria board support issues. To subscribe send an empty email to: avila-subscribe@lists.gateworks.com then confirm with a reply email. You can then post and view messages on the mailing list.
Hardware
Processor - Intel IXP43x
http://developer.intel.com/design/network/products/npfamily/ixp43x/docs.htm
Flash - Intel PC28F64P33B85, PC28F128P33B85, PC28F256P33B85
http://developer.intel.com/design/flcomp/prodbref/306782.htm
Ethernet LAN – National DP83848 http://www.national.com/pf/DP/DP83848K.html
Serial EEPROM - Philips Semiconductor PCF8594 http://www.semiconductors.philips.com/
Temperature and Voltage Monitor - Analog Devices AD7418 http://www.analog.com/
Software
Linux http://www.linux.org/
RedBoot http://sources.redhat.com/redboot/
Gateworks Board Support Package http://bsp.gateworks.com
Intel IXP4xx Software - VxWorks, Windows CE.NET, Linux http://developer.intel.com/design/network/products/npfamily/download_ixp400.htm
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4. SPECIFICATIONS 4.1. Electrical
Parameter Operating Voltage
Specification
Min Max
Input Voltage 8VDC 48VDC
Digital I/O – VIH 2.0VDC
Digital I/O – VIL 0.8VDC
Digital I/O – VOH (IOH = -16mA) 2.0VDC
Digital I/O – VOL (IOL = 16mA) 0.4VDC
Parameter Operating Current
Specification
Typ
Input Current (no Mini-PCI cards) 0.2A @ 24VDC
4.2. Environmental
Parameter Specification
Operating Temperature -40 to +85C
Storage Temperature -40 to +85C
Non-condensing Relative Humidity Less than 95% at 40C
Mean Time Between Failure 200 years at 55C
4.3. Mechanical
Parameter Specification
Dimensions, Length x Width 3.3 x 4.0 inches (84 x 102mm)
Dimensions, Height 0.7 inches (18mm)
Weight 3 ounces (85g)
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0.0
0 [0.0
0]
0.00 [0.00]0.20 [5.08]
0.2
0 [5.0
8]
0.7
0 [17.7
8]
1.4
4 [36.5
8]
2.1
1 [53.4
7]
3.1
0 [78.7
4]
3.3
0 [83.8
2]
0.50 [12.70]
0.85 [21.65]
2.39 [60.72]
3.80 [96.52]4.00 [101.60]
0.07 [1.75]
Ø0.125[3.18] HOLE
Ø0.250[6.35] PAD
(4 PLACES)
2.10 [53.34]
3.1
0 [78.7
4]
Ø0.109[2.77] HOLE
Ø0.180[4.57] PAD
Mechanical Dimensions
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5. CUSTOMER SUPPORT
5.1. Product Revision History
Revision A – Prototype Release (ECO 10000679 dated 04/07) The GW2350 was initially released at revision A with the printed circuit board at revision 01210067-00.
Revision B – Production Release (ECO 10000843 dated 06/08) Changes made to the GW2350 revision B include (1) add digital I/O to mini-PCI sideband signals to support mezzanine expansion boards such as GSM Modem and (2) correct IXP435 watchdog timer circuit.
Revision C – Production Release (ECO 10000869 dated 09/08) The primary change made to the GW2350 revision C was to change the 3.3V primary switcher bypass connector with an auxiliary input power connector.
5.2. Technical Assistance Gateworks technical support staff is available to assist you with questions that you may have. Please contact Gateworks using one of the methods shown below. Phone: (805) 781-2000 Fax: (805) 781-2001 Email: support@gateworks.com Website: http://www.gateworks.com
5.3. Warranty Standard hardware warranty period is ONE year from date of purchase. Gateworks will, solely at its option, repair or replace products, which prove to be defective in materials or workmanship, provided they are returned to a Gateworks authorized repair center. Shipment to Gateworks is at the customer's expense. Gateworks pays return shipment by ground. Products, which in Gateworks opinion, have been subject to misuse, abuse, neglect or unauthorized alteration or repair are excluded from this warranty. Products not manufactured by Gateworks are limited to the warranty provided by the original manufacturer and should be returned to the manufacturer in case of defect. Software is licensed AS IS. If for any reason, you are dissatisfied with the software return to Gateworks within 90 days for a full refund. The liability of Gateworks under this agreement is limited to a refund of the purchase price of the product. In no event shall Gateworks be liable for loss of profits or other damage.
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5.4. Return for Repair You must obtain a Returned Material Authorization (RMA) number before sending any product to Gateworks. Please contact Gateworks using one of the methods shown below to obtain an RMA number. Please be ready with your name, telephone number, company name, company address, shipping address, invoicing address, product number, and a technical description of the problem. A service charge will be applied to units that are out of warranty. Please pack the unit being returned in anti-static material and ship in a sturdy cardboard box with adequate packing material. Mark the RMA number clearly on the outside of the box before returning. Phone: (805) 781-2000 Fax: (805) 781-2001 Email: support@gateworks.com Website: http://www.gateworks.com Address: 3026 South Higuera Street, San Luis Obispo, CA 93401
5.5. Life Support Policy Gateworks products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of Gateworks Corporation. Refer to the following for definitions of critical components and life support devices.
1. A critical component is any component of a life support device or system whose failure to perform can be expected to cause the failure of the life support device or system, affect its safety, or limit its effectiveness.
2. Life support devices or systems are devices or systems which support or
sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
5.6. Copyright & Trademarks Specifications are subject to change without notice. All brand names or product names mentioned are trademarks or registered trademarks of their respective proprietors. END OF DOCUMENT