1Breaking the Cost Barrier

Breaking the Cost BarrierBreaking the Cost Barrier

Low-Cost, High-Speed

Programmable Solutions

No Compromises

2Breaking the Cost Barrier

Xilinx Breaks the Xilinx Breaks the Programmable LogicProgrammable Logic

Cost BarrierCost Barrier

Device cost

* 100K units, slowest speed, lowest density, cheapest package, mid-1999

Programmable logic is the most cost-effective logic solution!

Features

Performance In-system re-programmable FPGA RAM Boundary scan Low power

>100 MHz

FPGAs <$3* CPLDs near $1*

3Breaking the Cost Barrier

Programmable Logic Reduces Programmable Logic Reduces AllAll Cost Factors Cost Factors

Development system NRE Learning time Design time Risk Flexibility Testing Time-to-market

Starts at $95 $0 Hours Hours to days Zero with Core solutions Low Reprogram (even over web) 100% factory tested Days to weeks

4Breaking the Cost Barrier

Agenda:Agenda:Breaking the Cost BarrierBreaking the Cost Barrier

Example design challenge - PC99— solution alternatives

FireWire interface challenge— SpartanXL FPGA solution— Foundation software solution

SDRAM controller challenge— XC9500XL CPLD solution— Foundation and WebFITTER software

5Breaking the Cost Barrier

High Volume, Cost Sensitive High Volume, Cost Sensitive Challenges Are MetChallenges Are Met

Programmable solutions now meet high-volume needs — low cost — fast time-to-market

Example applications— consumer products— personal computers— PC peripherals

PC standards drive these applications— measure the solution against PC requirements

6Breaking the Cost Barrier

Example ApplicationsExample Applications

Digital audio mixing desks

Web TVsNetwork computers

Cell phones

Video phones

Security systems

Process controllersInternet appliances

Digital TV

Set-top boxes

Credit card readers

Graphics accelerationDVD

Hard drives

Printers

Voice processing

Digital cameras

Fax machines

PCI

USB

Medical imaging

Test equipment

PC99

Satellite base stations

Personal digital assistants GPS

Automotive cabin controlsCopiers

PCS phonesNetwork interface cards

Modems

Handsets

I/O interface boards

ADSL

PC Peripherals

SDRAM Controllers

Gate array replacement

Discrete logic integration

Badge readers

Arcade games

DSP

Ethernet adapters

Compact PCI

PCMCIA

IIC

Reconfigurable computing

Flight simulators

RAID

ISDN

Modems

Video editing

MPEG/JPEG

Bar code readers

Color correction

Network routers

Hubs

PBX switches Fiber optics

Click drivesVideo capture cards

Video compression

RISC interfaceSatellite decoders

Robotics

Mobile computing

PCS ground stations

Electronic toys

Device bay

Cable modems

PC network cards

Video cameras

Home theatre

Optical drives

POS terminalsCDROM drives

Digitizers

Imaging systems

Telephony

Audio

Digital VHS

Digital Hi-FiDSS

Digital monitorsCard bus

CAN bus

Video conferencing

Video conferencing

LANs

Network computers

Music synthesizers

Camcorders

Household appliances

FireWire

Multimedia

LCD projectors Monitors

Docking stations

Consumer electronics

Personal electronics

Handheld scanners

Instrumentation

Security systems

HDTV

VCR

7Breaking the Cost Barrier

Programmable Logic Challenge Programmable Logic Challenge PC99 ExamplePC99 Example

Intel/Microsoft guidelines for PCs built 1999-2000

Minimum 300 MHz processor, 32 MB RAM

Eliminates ISA bus— 12 MHz USB ports for mouse, keyboard— 400 Mbps FireWire ports for drives, audio, and video— Device Bay recommended for upgrading USB or FireWire

peripherals without opening the box

Mobile PC requires small size, low power

8Breaking the Cost Barrier

Xilinx Solution for PC99 Xilinx Solution for PC99 in PCs and Peripheralsin PCs and Peripherals

Processor

Personal ComputerPersonal Computer

Peripherals

SpartanXLUSB interface/

FireWireinterface

SpartanXLUSB interface/

FireWireinterface

Dev

ice

Bay

MemoryXC9500XLSDRAM

Controller

USB,FireWire

interfaces

USBUSBFireWireFireWire

9Breaking the Cost Barrier

FPGAs and CPLDs OftenFPGAs and CPLDs OftenCo-Exist in the Same SystemCo-Exist in the Same System

FPGAs excel at:— higher density— pipelined logic— FIFOs, register files

– using RAM

CPLDs excel at:— deterministic performance— fast pin-to-pin speed— state machines— wide decoding

10Breaking the Cost Barrier

CPLDs

FPGAs

Xilinx Low-Cost SolutionsXilinx Low-Cost SolutionsSpan the Density RangeSpan the Density Range

11Breaking the Cost Barrier

FPGA ChallengeFPGA ChallengeFireWire ExampleFireWire Example

FireWire part of PC99 spec is used to demonstrate the benefits of Xilinx FPGAs

IEEE 1394 standard— based on Apple’s original definition of FireWire

High speed serial bus— 400 Mbits/s required for PC99; increasing to 3.2 Gbits/s

For emerging consumer electronics— digital camcorders, DVD players, digital VCRs, HDTV,

set-top boxes, video conferencing

For traditional PC peripherals— hard drives, printers, scanners, modems

12Breaking the Cost Barrier

PhysicalLayer

PhysicalLayer

400 MHz

FireWire

ReceiveReceive50 MHzLink Layer Interface

FireWire Link Layer Interface FireWire Link Layer Interface Transmit SectionTransmit Section

TransmitTransmit8

App

licat

ion

Inte

rfac

e

CRC

CycleStart Core

StateMachine

FIFOsRequest/

Data

PHYInterface

Physical layer operates at full 400 MHz data transfer rate— serial-to-parallel conversion drops data rate to 50 MHz

for back-end link layer

Link Layer includes CRC generation and FIFOs

13Breaking the Cost Barrier

Challenges Facing the Challenges Facing the Design EngineerDesign Engineer

Design complexity

Flexibility for an evolving standard

Design cycle time

HDL entry

Cost control

High performance FIFOs

Design time

Design tools Low power

14Breaking the Cost Barrier

Potential SolutionsPotential Solutions Discrete logic

— not practical approach any longer— few available 3.3V/2.5V devices available

Chip sets— few available— expensive

Custom ASIC— long design cycle— costly to rework

Programmable Logic

15Breaking the Cost Barrier

Spartan Series FPGAs Spartan Series FPGAs Provide SolutionProvide Solution

Reprogrammable: instant updatesFlexibility and design complexity

— feature-rich programmable architecture

High performance: >100 MHz parallel logicDesign tools

— established, easy-to-use development tools— complete software support and extensive cores (IP)

Cost control— advanced process technology for small, low cost die— streamlined manufacturing provides total cost management

16Breaking the Cost Barrier

Xilinx FPGA Architecture Xilinx FPGA Architecture BenefitsBenefits

SRAM programming cells— easy design changes

On-chip distributed SelectRAM memory— efficient FIFOs

Segmented routing— high speed and low power

Dedicated carry logic— high speed counters and arithmetic

17Breaking the Cost Barrier

ReprogrammabilityReprogrammability

Fast time to market— immediate design changes— no cost penalty for mistakes and updates

Immediate production— no conversion costs— off-the-shelf— no inventory risk

100% tested— streamlined Xilinx testing reduces costs

18Breaking the Cost Barrier

High Performance FIFOsHigh Performance FIFOsUsing SelectRAM MemoryUsing SelectRAM Memory

Any logic block can be used as SelectRAM memory

Distributed RAM provides high performance solutions

Features— synchronous write,

asynchronous read— separate read port

in dual-port mode for FIFOs

19Breaking the Cost Barrier

2 bits2 bits32 bits32 bits

A0A1A2A3A4

O1

D Q

D Q

Q1

Q2

CLB CLB

D1

D2

WE CLK

D1 Logic

CLB RAM Provides 16xCLB RAM Provides 16xthe Storage of Flip-Flopsthe Storage of Flip-Flops

Configurable Logic Block (CLB) storage:— SelectRAM: 32 bits per CLB— flip-flops: 2 bits per CLB

100-784 CLBs in SpartanXL series

20Breaking the Cost Barrier

Short interconnect segments are combined to create custom routing paths automatically

Minimizes capacitance— higher speed & lower power

Internal three-state buffers for integrated buses

Dedicated clock routing for high speed and low skew

High Speed & Low Power High Speed & Low Power Through Segmented RoutingThrough Segmented Routing

CLBCLB

CLBCLB

CLBCLB

CLBCLB

Lo

ng

Lin

es

General Purpose SwitchMatrix

SwitchMatrix

21Breaking the Cost Barrier

All Xilinx FPGAs minimize power by using segmented interconnect

3.3V SpartanXL FPGAs consume less than half the power of 5V Spartan FPGAs

Power Down mode reduces quiescent current to 100 A

SpartanXL Low PowerSpartanXL Low Power

Spartan Spartan XL PowerDown

22Breaking the Cost Barrier

Fast Arithmetic and CountersFast Arithmetic and Counters

Increased arithmetic density and speed— dedicated carry logic in CLBs— dedicated carry routing— 16 bits at 120 MHz

DSP functions more efficient in FPGAs than dedicated DSP processors— twice the speed— one-tenth the cost

CLB

carry

CLB

carry

23Breaking the Cost Barrier

SpartanXL 3.3-V SeriesSpartanXL 3.3-V Series

No Compromises

XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL

System Gates 2K-5K 3K-10K 7K-20K 10K-30K 13K-40K

Logic Cells 238 466 950 1368 1862

Max Logic Gates 3,000 5,000 10,000 13,000 20,000

Flip-Flops 360 616 1120 1536 2016

Max I/O 80 112 160 192 224

Performance 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz

Config PROM 17S05XL 17S10XL 17S20XL 17S30XL 17S40XL

XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL

System Gates 2K-5K 3K-10K 7K-20K 10K-30K 13K-40K

Logic Cells 238 466 950 1368 1862

Max Logic Gates 3,000 5,000 10,000 13,000 20,000

Flip-Flops 360 616 1120 1536 2016

Max I/O 80 112 160 192 224

Performance 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz

Config PROM 17S05XL 17S10XL 17S20XL 17S30XL 17S40XL

24Breaking the Cost Barrier

SpartanXL ImplementationSpartanXL Implementation

Implement FIFO part of FireWire design as an example

50 MHz required

25Breaking the Cost Barrier

Equations/Schematic;Single designer

Timing-Driven Place and Route

VHDL orVerilogSynthesis;Single designer

HDL BackAnnotation

Synthesis and Cores;Small team

Tighter ties with synthesis vendors

Cores, HDL,Design reuse,Behavioral compiler;Larger design teams

Module Compile

Module Guide

Evolution of Programmable Logic Tools

Xilinx Design Tools Support Xilinx Design Tools Support Your MethodologiesYour Methodologies

TIMELINE Future

Evolution of Programmable Logic Design

26Breaking the Cost Barrier

Ready-to-Use

Push-button, high-performance design

Mixed-level design— easy schematic entry— superior HDL solution

Low-cost Base system supports all SpartanXL and XC9500XL devices

Xilinx Foundation SeriesXilinx Foundation Series

27Breaking the Cost Barrier

Instant ProductivityInstant Productivity Intuitive GUIs, with

design wizards

Mixed-level, mixed-language design environment

Push-button design flows

Intuitive project management

Demo

28Breaking the Cost Barrier

Best-in-ClassBest-in-ClassEDA TechnologyEDA Technology

Synopsys Synthesis

Xilinx Implementation tools (including A.K.A. Speed

Technology)

Aldec Design Entry Tools

Optional RTL HDL Simulation

Aldec Gate-Level Simulator

K-Paths Enhanced Static Timing

Analyzer

Demo

29Breaking the Cost Barrier

Unified Design EnvironmentUnified Design Environment

Design File Management

Window with File, and Version Tabs

Foundation Flow Engine Window

with Content, and Report Tab

Standard Windows Pull-down

Menus

Console Window with Error, Warning, and

Messages Tabs

Standard Windows Tool Bar

Status Indicator

Flow Button

Demo

30Breaking the Cost Barrier

On-line help includes link to support.xilinx.com— dedicated support web site— result of Silicon

Xpresso initiative

Foundation On-Line HelpFoundation On-Line Help

Demo

31Breaking the Cost Barrier

Graphical State Editor

Language Assistant

Graphical State EditorGraphical State Editor

Language AssistantLanguage Assistant

Superior HDL Solution Superior HDL Solution Design CreationDesign Creation

VHDL & Verilog HDL Design Capabilities Including:— graphical state diagram editor— powerful HDL editor with

integrated language assistant— LogiBLOX and CORE

Generator instantiations

HDL tutorials from Esperan

Xilinx Verilog CBT course

Demo

32Breaking the Cost Barrier

Design Wizard automates the

process of adding an HDL symbol

into a schematic.

Design Wizard automates the

process of adding an HDL symbol

into a schematic.

HDL Design becomes as easy as schematic entry with drop in

blocks of HDL.

HDL Editor directly associated with new schematic object

Mixed-Level DesignMixed-Level Design

HDL Design becomes as easy as schematic entry with drop in

blocks of HDL.

HDL editor directly associated with new schematic object.

HDL Design becomes as easy as schematic entry with drop in

blocks of HDL.

HDL editor directly associated with new schematic object.

Demo

33Breaking the Cost Barrier

XX

Foundation “Pull Automation” runs both Synthesis and Implementation tools after the push of a single button and completion of the synthesis / implementation dialog.

Optional HDL constraint entry and TimeTracker GUIs illustrate estimates of your design’s critical paths using an intuitive spreadsheet format

or

Push-Button SynthesisPush-Button Synthesis

Demo

34Breaking the Cost Barrier

Push-Button PerformancePush-Button Performance

Xilinx A.K.A. Speed technology— high quality of results— short run time

Demo

35Breaking the Cost Barrier

Design ResultsDesign Results

All constraints were met.

Timing summary:

Timing errors: 0 Score: 0

Constraints cover 1649 paths, 94 nets, and 516 connections (100.0% coverage)

Design statistics:

Minimum period: 19.025ns (Maximum frequency: 52.562MHz)

Demo

36Breaking the Cost Barrier

Beyond Push-Button Beyond Push-Button ImplementationImplementation

FPGAs allow for extensive optimization through creative design and implementation

Standard library counter runs at 120 MHz in SpartanXL using default options

Asynchronous frequency counter runs at over 400 MHz!— Uses extensive pre-scaling

37Breaking the Cost Barrier

AllianceCORE SolutionsAllianceCORE Solutions Core solutions leverage the optimization and

verification of third parties

FireWire AllianceCORE design and evaluation board available from Integrated Intellectual Property

Fully tested and verified for Xilinx FPGAs— pennies per

chip in volume

A

pplic

atio

nIn

terf

ace

CRC

CycleStart

RegisterSet

CRC Check

CoreState

Machine

FIFOsRequest/

Data

PHYInterface

Data

Status

PacketAnalyzer

38Breaking the Cost Barrier

Free Software & Free Cores Included (Cores offer over 1,000,000 permutations!)

Data sheets

CoreLINX:Web Mechanism to Download New Cores

SystemLINX:Third Party System Tools Directly LinkedWith Core Generator

Parameterized Cores

Core Generator Core Generator Delivery SystemDelivery System

Demo

39Breaking the Cost Barrier

PCI32 Spartan - Lowest Cost PCIPCI32 Spartan - Lowest Cost PCI

Standard Chip

External PLD7K Gates

7K Gates Logic

Com

pone

nt c

ost 1

00K

uni

ts

Standard ChipPCI Master I/F

XCS20XL-4 TQ144*

Solution <$7Solution <$7

PCI Master I/F

* Supported devices:XCS20XLXCS30XLXCS40XL

Power by$5

$20

$10

$15

40Breaking the Cost Barrier

High-Value Applications High-Value Applications with Spartanwith Spartan

*Prices are for 100K units, plastic package

XCS30XL Percentage of EffectiveCore Function Price Device Used Function Cost

UART $6.95 17% $1.20

16-bit RISC Processor $6.95 36% $2.60

16-bit, 16-tapSymmetrical FIR Filter $6.95 27% $1.90

Reed-Solomon Encoder $6.95 6% $0.45

LogiCORE PC132 Spartan(in PQ208) $8.25 45% $3.80

41Breaking the Cost Barrier

SpartanXL BenefitsSpartanXL Benefits

Fast time-to-market— user programmable

Low cost

Features for complex logic— high speed— low power

Easy to use— fully supported by Xilinx and third-party software

42Breaking the Cost Barrier

CPLD Solution for PC99 CPLD Solution for PC99 SDRAM Controller ExampleSDRAM Controller Example

Processor

Personal ComputerPersonal Computer SpartanXLUSB interface/

FireWireinterface

SpartanXLUSB interface/

FireWireinterface

Dev

ice

Bay

MemoryXC9500XLSDRAM

Controller

USB,FireWire

interfaces

USBUSBFireWireFireWire

43Breaking the Cost Barrier

Challenges Facing the Challenges Facing the Design EngineerDesign Engineer

100 MHz minimum speed

Multiple SDRAM protocols

Sufficient address width

Clock flexibility

Resources for future expansion

Small package

HDL entry

Cost control

Minimal programming overhead

Board layout before design is complete

Design time

Three-state flexibility

3.3V/2.5V

44Breaking the Cost Barrier

Memory Interface Memory Interface Block DiagramBlock Diagram

SDR

AM

s

Clock

WriteReset

Address[23:0] Address[11:0]

CSRASCAS

WE

Data[15:0]

Complete SDRAM Controller in a single CPLD

Mic

ropr

oces

sor

CPLD SDRAM Controller

45Breaking the Cost Barrier

SDRAM Interface Close-upSDRAM Interface Close-up

Address[23:0]

Data[15:0]

ADDR[11:0]

Clock

Reset

Write

CS

RAS

CAS

WE

ADDR[23:12]

ADDR[11:0]

Refresh Counter

Address DecodeChip

SelectMode

Register

State Machine

46Breaking the Cost Barrier

3.3-V XC9500XL Solution3.3-V XC9500XL Solution

Optimized for 3.3-V systems— compatible levels with 5.0/2.5V— no power sequencing restrictions!

Meets performance requirements— high fMAX = 200 MHz— fast tPD = 4 ns

Best ISP/JTAG support in industry

Best pinlocking in industry

Advanced packaging - New CSPs !

47Breaking the Cost Barrier

XC9500XL ArchitectureXC9500XL ArchitectureNew extra-wide function block inputs

48Breaking the Cost Barrier

XC9500XL Function BlockXC9500XL Function Block

Handles SDRAM address width with 54 inputs— highest function block fan-in on fast CPLDs

49Breaking the Cost Barrier

XC9500XL MacrocellXC9500XL Macrocell

Local macrocell clock inversion control

Flexible clocking and three-state control

50Breaking the Cost Barrier

XC9500XL Special XC9500XL Special System Designer BenefitsSystem Designer Benefits

Input hysteresis

Fully compliant ISP/JTAG guarantees no ISP lock out

No power sequencing restrictions

Hot plug-in

51Breaking the Cost Barrier

Advanced CSP PackagingAdvanced CSP Packaging

Supports high-growthmarket segments:Communications,Computers, Consumer

Uses standard IRtechniques for mounting

to PC board

52Breaking the Cost Barrier

XC9500XL Solution XC9500XL Solution Meets Design ChallengesMeets Design Challenges

3.3/2.5V electrical compatibility— no power-sequencing restriction

Chip scale packaging

Pin-locking allows design change flexibility

No programmer necessary with JTAG-based programming

Fast design time

VHDL, Verilog or ABEL design entry

53Breaking the Cost Barrier

100 MHz minimum speed— 133 MHz met

Multiple SDRAM protocols— 48% remaining capacity

Sufficient address width (32 or 64 bit)

Any clocking and three-state option needed

Abundant resources for future expansion

Low cost

XC9500XL Solution XC9500XL Solution Meets Design ChallengesMeets Design Challenges

54Breaking the Cost Barrier

XC9500XL 3.3-V FamilyXC9500XL 3.3-V Family

XC9536XL XC9572XL XC95144XL XC95288XL

Macrocells 36 72 144 288Usable Gates 800 1600 3200 6400tPD (ns) 4 5 5 6fMAX (MHZ) 200 178 178 151Packages 44PC 44PC QFP 64VQ 64VQ

100TQ 100TQ 144TQ 144TQ

208PQ

CSP/BGA 48CS 48CS 144CS 256BG

XC9536XL XC9572XL XC95144XL XC95288XL

Macrocells 36 72 144 288Usable Gates 800 1600 3200 6400tPD (ns) 4 5 5 6fMAX (MHZ) 200 178 178 151Packages 44PC 44PC QFP 64VQ 64VQ

100TQ 100TQ 144TQ 144TQ

208PQ

CSP/BGA 48CS 48CS 144CS 256BG

55Breaking the Cost Barrier

XC9500XL Design Software XC9500XL Design Software

XC9500XL fitters in all Xilinx standard software packages

Support for schematics, Verilog, VHDL, ABEL— Exemplar, Synopsys, Synplicity, and others

JTAG downloader for both FPGAs and CPLDs

WebFITTER simplifies test-driving CPLDs

Demo

56Breaking the Cost Barrier

Design in VHDL, Verilog, ABEL,

etc.

Submit designto WebFITTER

Evaluateresults

1 2 3

Demo

CPLD Design CPLD Design on the Webon the Web

No software to load— no user resources needed— no license

WebFITTER software always current— no upgrade CDs

Runs fast on network (minutes)

57Breaking the Cost Barrier

WebFITTER Intro PageWebFITTER Intro Page

Demo

58Breaking the Cost Barrier

WebFITTER Activity ReportWebFITTER Activity Report

Demo

59Breaking the Cost Barrier

WebFITTER Report FileWebFITTER Report File

Demo

60Breaking the Cost Barrier

SDRAM Controller SDRAM Controller Implementation in XC9500XLImplementation in XC9500XL

Results for XC95144XL

Utilization— 52% of capacity available for other logic

Speed— faster than required for 133 MHz clock

Lowest-cost solution

Compare to chip sets and other CPLDs

Demo

61Breaking the Cost Barrier

Simple & Fast Simple & Fast Low-Cost CPLD SolutionsLow-Cost CPLD Solutions

Isolates user from interface issues— critical signal timing— electrical interfacing— control signal sequencing (state machine design)

Variances In InterfacesSDRAM (i.e. Bank vs. SIMM)Unique System Back-End

62Breaking the Cost Barrier

New XC9500XV 2.5V FamilyNew XC9500XV 2.5V Family

XC9500XV 9536XV 9572XV 95144XV 95288XV

Macrocells 36 72 144 288Usable Gates 800 1600 3200 6400tPD (ns) 1H99 5 7 10 10 2H99 3.5 4 4 5fSYSTEM 200 178 178 151Packages 44PC (34) 44PC (34)(Max. User 64VQ (36) 64VQ (52) I/Os) 100TQ (72) 100TQ (81)

144TQ (117) 144TQ (117)208PQ (168)

BGA 256BG (168) CSPs 48CS (36) 48CS (36) 144CS (117)

63Breaking the Cost Barrier

Example ApplicationsExample Applications

Digital audio mixing desks

Web TVsNetwork computers

Cell phones

Video phones

Security systems

Process controllersInternet appliances

Digital TV

Set-top boxes

Credit card readers

Graphics accelerationDVD

Hard drives

Printers

Voice processing

Digital cameras

Fax machines

PCI

USB

Medical imaging

Test equipment

PC99

Satellite base stations

Personal digital assistants GPS

Automotive cabin controlsCopiers

PCS phonesNetwork interface cards

Modems

Handsets

I/O interface boards

ADSL

PC Peripherals

SDRAM Controllers

Gate array replacement

Discrete logic integration

Badge readers

Arcade games

DSP

Ethernet adapters

Compact PCI

PCMCIA

IIC

Reconfigurable computing

Flight simulators

RAID

ISDN

Modems

Video editing

MPEG/JPEG

Bar code readers

Color correction

Network routers

Hubs

PBX switches Fiber optics

Click drivesVideo capture cards

Video compression

RISC interfaceSatellite decoders

Robotics

Mobile computing

PCS ground stations

Electronic toys

Device bay

Cable modems

PC network cards

Video cameras

Home theatre

Optical drives

POS terminalsCDROM drives

Digitizers

Imaging systems

Telephony

Audio

Digital VHS

Digital Hi-FiDSS

Digital monitorsCard bus

CAN bus

Video conferencing

Video conferencing

LANs

Network computers

Music synthesizers

Camcorders

Household appliances

FireWire

Multimedia

LCD projectors Monitors

Docking stations

Consumer electronics

Personal electronics

Handheld scanners

Instrumentation

Security systems

HDTV

VCR

64Breaking the Cost Barrier

High-Volume FPGA High-Volume FPGA Price LeadershipPrice Leadership

100k unit volume price projections

New Applications• Set Top Box• DVD• Digital Camera• PC Peripherals• Consumer Electronics

New Applications• Set Top Box• DVD• Digital Camera• PC Peripherals• Consumer Electronics

Den

sit

y (S

yst

em G

ates

)

1997 1998 1999 2000 2001 2002

15k

40k

100k

60k25k

60k

200k

100k

10K Gates Per Dollar in 2002!10K Gates Per Dollar in 2002!

$20

$10

65Breaking the Cost Barrier

* Prices are based on 100ku+, slowest speed grade, lowest cost package

CPLD Price LeadershipCPLD Price LeadershipNo Compromises Flexible ISP tPD = 4ns (‘99); 2.5ns (‘02) Best Pin-Locking Industry Standard JTAG 2.5V (0.25 Flash) in 1999

No Compromises Flexible ISP tPD = 4ns (‘99); 2.5ns (‘02) Best Pin-Locking Industry Standard JTAG 2.5V (0.25 Flash) in 1999

$0.90$1.00$1.20

$0.85

$4.50$3.95

$3.25

$2.95

$6.00

$7.00

$8.00

$9.00

0

1

2

3

4

5

6

7

8

9

10

1999 2000 2001 2002

XC9536XX XC95144XX XC95288XX

66Breaking the Cost Barrier

Solutions for Low-Cost, Solutions for Low-Cost, High-Volume ApplicationsHigh-Volume Applications

Low cost programmable logic— SpartanXL FPGAs available— XC9500XL CPLDs available

High performance System-level features Ease of evaluation and design

— WebFITTER, Foundation 1.5i software available