Post on 03-Apr-2018
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ARM INSTRUCTIONS
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• Being a RISC architecture it has only Load
Store type instructions.
• Data is manipulated within registers
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• Data Processing Instructions
– MOVE instructions
– Arithmetic Instructions
• Multiply Instructions
• Logical Instructions
• Comparison Instructions
• Suffix S on data processing instructions
updates flag in CPSR.
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• Instructions are 32 –
Bit wide; comes fromregisters or specified as literals in instruction
itself
•Second operand sent to ALU via Barrel Shifter
• 32 – Bit wide result placed in register ; long
multiply instruction produces a 64 – Bit result
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• Move Instructions
• MOV Rd,N
– Rd : Destination Register
– N : Can be immediate value or source register
– Example: mov r7,r5
• MVN Rd,N
• Move into Rd the not value of source
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• Using Barrel Shifter
– Enables 32 bit shifting in source registers left or
right by specific positions within the cycle time of
instruction
• Basic Barrel Shifter operations
• Shift Left• Shift Right
• Rotate Right
• Facilitates fast multiply, divide and hence increases code
density
• Example:
– Mov r7,r5,LSL#2
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•
Arithmetic Instructions – Implements 32 bit addition and subtraction
• 3 – operands form
• Example
– Sub r0,r1,r2
– Subs r1,r1,#2
• With Barrel Shifter
•add r0,r1,r1LSL#1
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• Multiply instruction
– Multiplies a pair of registers
– Long multiply generates a 64 bit result
• Examples:
• Mul r0,r1,r2
• Umul r0,r1,r2,r3 – Unsigned multiply with result stored in r0 and r1
• Multiply and Accumulate• MLA rd,rm,rs,rn
• Rd=(rm*rs) + rn
• UMLAL rdlo,rdhi,rm,rs• [Rdhi,rdlo] = [rdhi,rdlo] + (rm*rs)
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• Logical Instructions – Bitwise logical operations on two source registers
• AND, OR, XOR, bit clear
•
ExampleBIC r0,r1,r2
• Compare Instructions
– Comp r0,r9
– Teq r0,r9
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• Load Store Instructions
– There are 3 types of load store instructions
• Single register transfer
• Multiple register transfer
• Swap
–
LDR – LDRH
– LDRB
– STR
– STRH
– STRB
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•
Supports different addressing modes – Register indirect: LDR r0,[r1]
– Immediate: LDR r0,[r1,#4]
–
Register operation: LDR r0,[r1,-r2]• More Addressing Modes
• Scaled Addressing Modes
• Pre & Post Indexing
– Pre Index with write back: LDR r0,[r1,#4]
• Post Index: LDR r0,[r1],#4
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• Multiple Register Transfer
– Load – Store multiple instructions transfers
multiple register contents between memory and
processor in a single instruction
– More Efficient
– These instructions can increase interrupt latency
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• LDM
•
SDM – Mnemonics used for multiple data transfer