Post on 02-Jan-2016
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Agenda
Top-level architecture and attributes Configurable logic block Memory I/O block Three-state buses Clocks and delay-locked loops Power down mode Configuration
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The Leading Programmable Logic Solution for Consumer Electronics
Plentiful logic and memory resources
— 15K to 200K system gates (up to 5,292 logic cells)— Up to 57 Kb block RAM storage
Flexible I/O interfaces— From 86 to 284 I/Os — 16 signal standards
High performance— System frequency as high as 200 MHz
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Pricing for 250,000 units, end-2000, slowest speed, cheapest package
Complete Solution
Low power— Power down mode guarantees minimum power— 2.5-V core supply voltage
Programmable flexibility— Speeds time to market for your product
Lowest cost FPGAs in the industry— 100,000 system gate device for $10
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Spartan-II Top-level Architecture
Configurable logic blocks— Implement logic here!
I/O blocks— Communicate with other
chips— Choose from 16 signal
standards
Block RAM— On-chip memory for
higher performance
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Spartan-II Top-level Architecture (cont’d)
Clocks and delay-locked loops— Synchronize to clock on
and off chip
Rich interconnect resources — Three-state internal
buses
Power down mode— Lower quiescent power
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Spartan-II Family OverviewDevice XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200
Logic Cells 432 972 1728 2700 3888 5292
Block RAM Bits 16,384 24,576 32,768 40,960 49,152 57,344
Block RAM Qty. 4 6 8 10 12 14
Max. User I/Os 86 132 176 196 260 284
Package VQ100 VQ100
CS144 CS144
TQ144 TQ144 TQ144 TQ144
PQ208 PQ208 PQ208 PQ208 PQ208
FG256 FG256 FG256 FG256
FG456 FG456 FG456
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CLB Slice (Simplified)
1 CLB holds 2 slices
Each slice contains two sets of the following:— Four-input LUT
– Any 4-input logic function– Or 16-bit x 1 RAM– Or 16-bit shift register
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CLB Slice (cont’d)
Each slice contains two sets of the following:— Carry & control
– Fast arithmetic logic– Multiplier logic– Multiplexer logic
— Storage element– Latch or flip-flop– Set and reset– True or inverted inputs– Sync. or async. control
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CLB
MUXF6
Slice
LUT
LUTMUXF5
Slice
LUT
LUTMUXF5
Dedicated Expansion Multiplexers
MUXF5 combines 2 LUTs to form— 4x1 multiplexer— Or any 5-input function
MUXF6 combines 2 slices to form— 8x1 multiplexer— Or any 6-input function
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CO
DI CIS
LUT
CY_MUX
CY_XOR
MULT_AND
A
B
A x B
Dedicated Multiplier Logic
Highly efficient ‘shift & add’ implementation— For a 16x16 multiplier
– 30% reduction in area– 1 less logic level
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D QCE
D QCE
D QCE
D QCE
LUT
INCE
CLK
ADDR[3:0]
OUT
Slice
LUT
LUT
Slice
LUT
LUT
CLB
0
1
2
15
Look-up Table Shift Registers
Each LUT can be configured as shift register— Serial in, serial out
Dynamically addressable delay up to 16 cycles
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Flexible Cycle Delays
Use for programmable clock delay
Cascade for greater cycle delays
Use CLB flip-flops to add depth
D QCE
D QCE
D QCE
D QCE
LUT
INCE
CLK
ADDR[3:0]
OUT
Slice
LUT
LUT
Slice
LUT
LUT
CLB
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200 MHz Memory Continuum
Highest performance FPGA memory system
bytes
16x1
DSP CoefficientsSmall FIFOsShallow/Wide
Distributed RAMkilobytes
4Kx12Kx21Kx4512x8
256x16
Large FIFOs Packet BuffersVideo Line BuffersCache Tag MemoryDeep/Wide
Block RAMmegabytes
SDRAMZBTRAMSSRAMSGRAM
External RAM
Memory Bandwidth and Flexibility
Spartan-II on-chip SelectRAM+TM memory
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Spartan-IIDual-R/W
PortBlock RAM
Port A
Port B
WR
WR
WR
RW Data Flow Spartan-II
A to B YesB to A YesA to A YesB to B Yes
Block RAM Provides 4K Bits Each
Dual read/write ports, each with:— Independent clock, R/W, and enable— Independently configurable data width from 4Kx1 to
256x16
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Block RAM Timing
Clock-to-output (glitch-free): 2.5 ns typ.
Address/data input setup: 1.0 ns typ.
Lookup table based RAM provides additional small memories (16x1)— Same timing as CLB logic
Both easily initialized at configuration to simulate ROM
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I/O Block (Simplified)
Registered input, output, 3-state control
Programmable slew rate, pull-up, pull-down, keeper and input delay
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I/O Interface Standards
I/O can be programmed for 16 different signal standards— VCCO controls maximum output swing— VREF sets input, output, three-state control
Different banks can support different standards at the same time— Logic level translation— Boards with mixed standards
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IOBs Organized As Independent Banks
As many as eight banks on a device— Package dependent
Each bank can be assigned any of the 16 signal standards
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Chip to ChipLVTTL, LVCMOS
Chip to MemorySSTL2-I, SSTL2-II, SSTL3-I,SSTL3-II, HSTL-I, HSTL-III,HSTL-IV, CTT
Chip to BackplanePCI33-5V, PCI33-3.3V, GTL, GTL+, AGP
Allows support for future standards!
SDRA
M
SSTL
GTL+
LVTTL
LVCMOSCTT
SRAM
HSTL
Spartan-II As Center forSignal Translation
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Performance Challenge Met by Spartan-II Speed
Consistently high performance across I/O signal standards
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Performance Challenge Met by Spartan-II Speed (cont’d)
Dedicated block RAM equals ASIC performance
Delay-locked loop maximizes internal & external performance
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2ns
2ns
2ns2ns
CLB Array
High Performance Routing
Hierarchical routing— Singles, hexes, longs
Sparse connections on longer interconnects for high speed
Routing delay depends primarily on distance— Direction independent— Device-size independent
Predictable for early design analysis
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Internal Three-state Buses
Two 3-state drivers per CLB
Permits using internal 3-state buses for a “system on a chip”
OR-AND logic implementation in place of 3-state drivers
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Internal Three-state Buses (cont’d)
Low power— No danger of contention when multiple BUFTs
enabled— No physical pullups or large capacitance to drive
With no drivers enabled, bus is a logic 1
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General Clock Support
Four dedicated global low skew buffers— Dedicated input pin (clock distribution only)— 66-MHz PCI with 500-ps maximum skew
– Input IOB flip-flop (no data delay): ts = 3 ns / th = 0 ns– Output IOB flip-flop: tco = 6 ns typ.
Additional shared resources (e.g., long lines)— Distribute low-skew/high-fanout signals (10 ns max.)
Four delay-locked loops on each device— Two global buffers associated with each DLL pair— All-digital implementation
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Delay-locked Loop Functions
Eliminate clock distribution delay for fast TCO
System synchronization (e.g., clock mirrors)
Phase-shifted clocks
Clock multiplication and division
Clean up clocks with 50/50 duty cycle correction
Clock lock for internal & external synchronization— DLL feedback connected internally or externally— Can synchronize configuration to DLL lock
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DLL Macros
Two DLL versions available— Controlled by macro choice
CLKDLL (low frequency) — Input frequency: 25 MHz to
100 MHz— All 6 outputs available
– CLK0, CLK90, CLK180, CLK270, CLK2X & CLKDV
CLKDLLHF (high frequency)— Input frequency 60 MHz to 200
MHz— 3 outputs available
– CLK0, CLK180 & CLKDV
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Output standard = LVTTL Fast 16mA
(OBUF_F_16)
Temp=room, Vdd=2.5V, Vcco=3.3V
Waveforms:
1: CLKIN
2: DATA OUT (no DLL)
3: DATA OUT (DLL deskewed)
Timing
w/o DLL w/ DLL
r->r r->f r->r r->f
3.6n 3.5n 1.4n 1.4n
Improved Clock-to-out Using DLL
Spartan-II clock-to-out delays reduced over 50%
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DLL1
DLL3
DeskewClockson Chip
Manage up to 4System Clocks
DeskewClocks
on Board
CascadeDLLs
GenerateClocks• multiply• divide• shift
ConvertClockLevelsusing
Select I/O
Delay locked loops synchronize on-chip and board level clocks
Spartan-II DLLs ImproveClock Networks
DLL4
DLL2
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Power-down Mode
Controlled by single power down pin
All inputs blocked, appear low internally
All outputs disabled
All register states preserved
Power-down status pin
Synchronous wake up
100 uA typical
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Mode
Config.Data
Format
Direction ofSynchronizing
Clock UseSlaveSerial
Serial FPGA receivesCCLK
Processor or CPLD or another FPGA ( in Mastermode) controls configuration of slave FPGA
Also for configuring multiple slave FPGAs in adaisy chain (2ND, 3RD FPGA, etc.).
MasterSerial
Serial FPGA generatesCCLK
FPGA in Master mode configures itself from aserial PROM.
Also, 1st FPGA (master) in daisy chain controlsconfiguration of slave FPGA(s) in a daisy chain.
SlaveParallel
Byte FPGA receivesCCLK
Processor or CPLD controls the fast configuration ofslave FPGA.
JTAG Serial FPGA receivesTCK
Make use of existing boundary scan port
There are four ways to program a Spartan-II FPGA
Configuration Modes
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Partial Reconfiguration
Frame by frame reconfiguration supported while device is running— Routing changes affect device operation— Re-initializing a block RAM requires stopping all
access in that column
Can dynamically load the required logic at a given time— Minimizes cost further by time-multiplexing the logic
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