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Dr. Rehan Hafiz Lecture # 03
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Course Website for ADSD Fall 2011
http://lms.nust.edu.pk/
Key: EE803
2
Lectures: Tuesday @ 5:30-6:20 pm, Friday @ 6:30-7:20 pm
Contact: By appointment/EmailOffice: VISpro Lab above SEECS Library
Acknowledgement: Material from the following sources has been consulted/used in theseslides:1. [SHO] Digital Design of Signal Processing System by Dr Shoab A Khan
Material/Slides from these slides CAN be used with following citing reference:Dr. Rehan Hafiz: Advanced Digital System Design 2010
Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License.
http://creativecommons.org/licenses/by-nc-sa/3.0/8/3/2019 ADSD Fall2011 03 Sequential Logic Blocking Non Blocking 30Sep11
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3
1 Introduction Outline & Introduction, Initial Assessment of students, Digital design
methodology & design flow2 Verilog+
Combinational Logic
Combinational Logic Review + Verilog Introduction, Combinational Building
Blocks in Verilog
3 Verilog + Sequential Logic Sequential Common Structure in Verilog (LFSR /CRC+ Counters + RAMS),
Sequential Logic in Verilog4 Synthesis in Verilog Synthesis of Blocking/Non-Blocking Statements5 Micro-Architecture Design Partitioning + RISC Microprocessor + Micro architecture Document6 Optimizing Speed Architecting Speed in Digital System Design: [Throughput, Latency, Timing]7 Optimizing Area Architecting Area in Digital System Design: [Area Optimization]8 FIR Implementation FIR Implementations + Pipelining & Parallelism in Non Recursive DFGs10 CDC Issues Cross-Clock Domain Issues & RESET circuits11 Fixed-Point Arithmetic Arithmetic Operations: Review Fixed Point Representation12 Adders Adders & Fast Adders Multi-Operand Addition13 Multipliers Multiplication , Multiplication by Constants + BOOTH Multipliers 13 CORDIC CORDIC (sine, cosine, magnitude, division, etc), CORDIC in HW
14 Algorithmic
Transformations for
System DesignDFG representation of DSP Algorithms, Iteration Bound
& Retiming
15 Algorithmic
Transformations for
System DesignUnfolding
Look ahead transformations16 Project Course Review & Project Presentations17 Project Project Presentations
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Suggested Reading
4
Sequential Logic
Section 3.1-3.3
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digital circuits that have
memory/storage
.the output is dependent not only on the
present inputs, but also on past inputs;
Sequential Logic Using Verilog - Review5
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Why avoid latches ?
6
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Storage Elements
7
SR Latch
Non Transparent D-Latch
D-Latch (Transparent)
Edge Triggered D Flip Flop
Register
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Latches
Level sensitive storage elements8
Feedback structure of crosscoupled Nor/Nand Gates
Two Stable outputsdepending on S & R
Note: Q & Q are not logicalcomplements
Problem
When S=R=1 Transition from 11 to 00
causes race condition(oscillations)
NOR
0 0 1
1 x 0
SR Latch
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Why avoid latches ?
9
0
1 0
1
0
1
Ideally the oscillations never stop
NOR
0 0 1
1 x 0
0
0 0
1
0
1
1
1 0
0
0
1
1
1 0
0
0
0
0
0 1
1
0
0
0
0 0
0
1
1
0
0 1
1
0
0
Practically due to gate delays oscillations will come to halt
Prev. Values
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Race Condition
Oscillations
10
0
0 1
1
0
0
Q
Q
0
0 0
0
1
1
Assignment: Simulate the SR latch with different gate delays
(2 different cases). Apply a sequence of SR values to
demonstrate the race condition.
Case a: Equal Gate Delays
Case b: Experiment with such a value of gate thatdemonstrates how the oscillation may end due to different
gat delays
LMS + Print of timing diagrams
http://www.verilogtutorial.info/chapter_2.htm
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A solution
Non Transparent D-Latch11
D
Gate delays can still cause race
condition (S=R=1)
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A Transparent D-Latch
or simply D-Latch12
Non Transparent: Data input Reset input connected with inverted Data (Set) input
Gate delays can still cause race condition (S=R=1)
Transparent
Latch is transparent to input only when Enable is set
So what's the problem now ?
D
S
D=R
En
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When to set enable ??
13
An enable signal that pulses at a constant rate
The Clock Signal
Synchronous Sequential Circuit
Storage elements that can update value only at a
clock
Asynchronous Sequential Circuit
A sequential circuit (or storage element) that doesnot uses clock
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So now we have a synchronous enable Clock
Any problem now ?14
D Q
E
D Q
E
D Q
E
D Q
E
D
Clk
Clk-A
Clk-B
How many D-Latches the data will pass through
--- while the clock is high
l l l
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Solution : D-Flip Flop
Edge Triggered15
l
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Storage Elements
Review16
SR Latch
Race Conditions
Simple D-Latch
Gate delays can still cause race condition
Transparent D-Latch
Defining the length of enable signal
Edge Triggered D Flip Flop
The MOST used storage element
Register
Multiple parallel D Flip Flops
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D Latch in Verilog(Asynchronous Sequential Logic)
17module d_latch (
input E,input DATA,
output reg Q,
);always @ (E or DATA)begin
if (E == 1'b1)Q
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D Latch in Verilog with
Asynchronous Reset18
module d_latch (input E,
input reset,
input DATA,
output reg Q,
);
always @ (E or DATA or rst_n)Begin
if (~rst_n) beginQ
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D Flip Flop in Verilog
Synchronous Sequential Logic19
module d_register
(input CLK,
input DATA,
output Q,
reg Q
);
always @ (posedge CLK)begin:Q
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ip op in eri ogSynchronous & Asynchronous Resets(Always use reset with feedback registers)
20
module d_register (rst_n, CLK,
DATA, Q);
input CLK, DATA, rst_n;
output reg Q;
always @ (posedge CLK)begin:
if (rst_n == 1b0)Q
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Generating Clock in stimulus
21
timescale 1ns/1ns
define PERIOD 5 // 100MHz clock
reg clk;
initialclk= 1b0;
always @ (clk)#PERIOD clk = ~clk;
initial
#1000 $finish;
Clock is not a normal signal
Not to be treated like a
normal reg/wire
Code Example : `timescale 1 ns /
10 ps
Indicates delays are in 1
nanosecond units with 2 decimalpoints of precision (10 ps is .01
ns).
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22
The Verilog hardware descriptionlanguage, Volume 1By Donald E. Thomas, Philip R. Moorby
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Generating RESET in stimulus
23
We must reset all the feedback registers inthe design.
Example Code
Reset (active low) the system after 5 time units: initial
begin
rst_n = 1b0;
# 5 rst_n = 1b1;
end
C di G id li
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24
[SHO]
Coding Guideline
ALWAYS RESET
Feedback Registers else
there shall be
uncertainties in yourdesign !
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Instantiating Memory Elements
25
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Block RAM Vs. Distributed RAM
26
Distributed RAM
Custom Memories created using LUT (for Xilinx)
Good for storing small amounts of data, making registers, shift registers, etc.
Block RAM
Dedicated, configurable memory with address, data, and control ports.
For large data storage
TIP
For larger memory; MUST use BRAM else the synthesizer will consume logic area of
FPGA meant for your actual LOGIC design.
Example: BRAM in Xilinxs Virtex-4 FPGAs
Consists of 16 kbits, blocks (16k single bits, 8k 2 bit words, up to 512 36-bit
words)
Blocks can be chained together to form large memories
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Register File
27
We need to have an addressable Register File
May be synthesized as Flip Flops or Distributed
RAM Depending standard or non-standard
accessing !
Not used for mass storage because they occupy
significantly more silicon area than compiled
memory Look for on-chip resources (Xilinx Block RAM &
Distributed RAM)
Register File
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Register File
Synthesis28
Example: 5.47[CIL]
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Remember
Verilog 2001 allows Multi-Dimentional Arrays
29
Xilinx allows supports upto 3D arrays
Declaring 3D array
//////////////// 3 D Array
reg [7:0] d [0:3][0:1][0:1];
Accessing 3D Array
d[i1][i2][i3]
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Blocking vs. Non Blocking Statements
Always Block
30
Non Blocking Statement
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Non Blocking Statement
31
Concurrent procedural assignments - Do not block the procedural flow
Behaviour of every statement needs to be implemented independently in parallel
Use -- whenever you want to make several parallel register assignments within the same
time step without regard to order or dependence upon each other Dependencies define the connectivity - only !
module blockingnonblocking (
output reg out,
input clk, in1, in2, in3);
reg logicfun;
always @(posedge clk) begin
logicfun
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Blocking Statement
32
Future operations are blocked until current operation has been completed.
Behaviour: All future operations are under the assumption that all
previous operations have completed and all variables have been updated Dependencies define the number of registers inferred
module blockingnonblocking (
output reg out,
input clk, in1, in2, in3);
reg logicfun;always @(posedge clk) begin
logicfun = in1 & in2;out = logicfun | in3;end
endmodule
There is a dependency.
out will not be updateduntil logicfun has been
updated, and both
updates must occur on
one event of the clock
& this is a confusing styleof coding Do Not Do
This !
Bl ki St t t
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Blocking Statement
33
Future operations are blocked until current operation has been completed.
Behaviour: All future operations are under the assumption that all
previous operations have completed and all variables have been updated Dependencies define the number of registers inferred
module blockingnonblocking (
output reg out,
input clk, in1, in2, in3);
reg logicfun;always @(posedge clk) begin
out = logicfun | in3;logicfun = in1 & in2;end
endmodule
There is no dependency within
the always block !
we force the out register to beupdated before logicfun, which forces
a 2-clock cycle delay for the inputs in1
and in2 to propagate to out.
S E l always @ (posedge c)
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Some more Examples34
always @ (posedge c)
Begin
p
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Blocking statements CAN result into registers if used with edge triggered
clock BUT Blocking statements SHOULD NOT be used for generating
sequential logic
In blocking statements order is important
35
always @ (posedge c)
Begin
z = b;
end
y @ ( )
Begin
z = b;
end
always @ (posedge c)Begin
r = b;
s=r;
z = s;
end
S
always @ (posedge c)
Begin
r = b;
z = s;
s=r;
end
Confusing
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Confusing
Very Simple Way out ?????36
Use blocking assignments to model
combinatorial logic
Use non-blocking assignments tomodel sequential logic (Also Latches)
Never mix blocking and non-blocking
assignments in one always blockThink HARDWARE
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More Sequential Circuits
37
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This Lecture
38
LFSR Linear Feedback Shift Register
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RTL Example: shift Register
39
clock
Data_in
R
QD
R
QD
R
QD
R
QD
reset
Data_out
module Shift_reg4 (output Data_out,
input Data_in,
input clock,
input reset);
reg [3: 0] Data_reg;
assign Data_out = Data_reg[3];always @ (negedge resetor posedge clock)
begin
if(reset == 1'b0) Data_reg
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LFSR Linear Feedback Shift
Register40
Efficient design for
Test Pattern Generators / Output Response Analyzers
Data Encryption
Considered efficient than counters
High Speed Memory Addressing when order is not important !
Loaded with pre-defined values on reset
Fig:4-2: A designer's guide to built-in self-test---- By Charles E. Stroud
One to Manyis better over
Many to One
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LFSR Characteristic Polynomial
41
Characteristic polynomial
Defined by XOR positions
Deg. of polynomial = No. of FF
For a degree 4 LFSR with all possible connectionsP(x) = x4+x3+x2+x+1Always present terms: Primary Feedback (x4) &
Principle Input (1 = x0 )
P(x) = x4+x3+ x+1 coefficient = 0 if no connection
coefficient = 1 if connection
Primitive Polynomials: Ensure all possible cases
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Primitive Polynomials: Ensure all possible cases
42
Autonomous LFSR
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Autonomous LFSR
Pseudo Random Number Generation43
Registers are preloaded with an initial seed
Taps Coefficients: C1, C2, C3,.., CN
C0=1
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Autonomous LFSR
44
Eight-Cell Autonomous LFSR
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Eight Cell Autonomous LFSR
Parameterized45
Serial Input Hardware
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Serial Input Hardware
Implementation of CRC-3246
LFSR Taps/Coefficients
1,2,4,5,7,8,10,11,12,16,22,23,26,32
Example CRC32 for a Network
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Example CRC32 for a Network
Packet Receiver47
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Using LOOPs
48
Useful for writing compact systematic code that is
easy to be de-bugged
Loops available: Repeat, While & For Loop
Syntax For (initial_statement; control_expression; index_statement)
Statement_for_exeecution
The loop determination must be a constant Ifits a variable, the size of the loop can not be
determined statically and thus the loop may not be
synthesize
Example- For loop based Decoder
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Example For loop based Decoder
49
module forloop(
output reg [7:0] yOut,
input [2:0] aIn,
input enable);
always@(aIn or enable)
begin
yOut = 8'b00000000;
case (aIn)
3'b000 : yOut[0] = 1'b1;
3'b001 : yOut[1] = 1'b1;
3'b010 : yOut[2] = 1'b1;
3'b011 : yOut[3] = 1'b1;
3'b100 : yOut[4] = 1'b1;
3'b101 : yOut[5] = 1'b1;
3'b110 : yOut[6] = 1'b1;
3'b111 : yOut[7] = 1'b1;
endcase
end
endmodule
module forloop(
output reg [7:0] yOut,
input [2:0] aIn,
input enable);
integer k;
always@(aIn or enable)
begin
for(k=0;k
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Example FOR Loops as an exhaustive test
vector generator50// Illustrates efficient way to exhaustively test
// a combinational circuit
module CombinationalCircuit_TB;reg a,b,d,c;wire y;// Instantiate the device-under-testCombinationalCircuit DUT (
.a(a),
.b(b),
.c(c),
.d(d),
.y(y));// Declare loop index variableinteger k;
// Apply input stimulusinitial begin{a,b,c,d} = 0;
for (k=0; k
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Modelling Digital Machines with Repetitive Algorithms
Repeat, While & For Loop
51
[CIL]
C di G id li f LOOP
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Coding Guidelines for LOOP
52
Do not put a semicolon after for loop
Do not use same control variable for multiple
loops
Use int for control variable
G d R MUST READ
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Good Resources MUST READ53
3 Articles related to LFSR by Clive Maxfield
Good discussion on Blocking/Non Blocking
Statement
Nonblocking Assignments in Verilog Synthesis,Coding, Styles That Kill!, Clifford E. Cummings
Sunburst Design, Inc.
All these shall be uploaded to LMS.
Please let me know if this does not happens
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Questions.