Post on 17-Dec-2015
ADC TYPES
EE174 – SJSULecture #4Tan Nguyen
Types of ADC
• Flash ADC• Successive approximation converter• Counter Ramp Converter• Integrating ADC
Flash ADC
• Also known as Parallel ADC• A n-bit flash ADC uses 2n-1 comparators and a encoder logic. • Advantage: the fastest type of ADC.• Disadvantages: limited resolution, expensive, large power
consumption and low accuracy.• Applications: Data acquisition, satellite communication, radar
processing, sampling oscilloscope and high density disk drives.
Flash ADC
3-bit flash ADC
Successive-approximation ADC
Start Conversion (SC)
A DAC is used to generate approximations of the input voltage.
A comparator is used to compare Vin and Vappr.
In each cycle, SAR finds one output bit using comparator.
To start conversion, set SC = 1. When conversion ends, EOC = 1.
Quite fast, expensive, high accuracy and one of the most widely used design for ADCs.
A DAC is used to generate approximations of the input voltage.
A comparator is used to compare Vin and Vappr.
In each cycle, SAR finds one output bit using comparator.
To start conversion, set SC = 1. When conversion ends, EOC = 1.
Quite fast, expensive, high accuracy and one of the most widely used design for ADCs.
Successive Approximation ADC Example
Goal: Find digital value Vin
• 8-bit ADC• Vin = 7.65
• Vfull scale = 10
Successive Approximation ADC Example
• MSB LSB• Average high/low limits• Compare to Vin
• Vin > Average MSB = 1
• Vin < Average MSB = 0
• Bit 7• (Vfull scale +0)/2 = 5• 7.65 > 5 Bit 7 = 1
Vfull scale = 10, Vin = 7.65
1
Successive Approximation ADC Example
• MSB LSB• Average high/low limits• Compare to Vin
• Vin > Average MSB = 1
• Vin < Average MSB = 0
• Bit 6• (Vfull scale +5)/2 = 7.5• 7.65 > 7.5 Bit 6 = 1
Vfull scale = 10, Vin = 7.65
1 1
Successive Approximation ADC Example
• MSB LSB• Average high/low limits• Compare to Vin
• Vin > Average MSB = 1
• Vin < Average MSB = 0
• Bit 5• (Vfull scale +7.5)/2 = 8.75• 7.65 < 8.75 Bit 5 = 0
Vfull scale = 10, Vin = 7.65
1 1 0
Successive Approximation ADC Example
• MSB LSB• Average high/low limits• Compare to Vin
• Vin > Average MSB = 1
• Vin < Average MSB = 0
• Bit 4• (8.75+7.5)/2 8.125• 7.65 < 8.125 Bit 4 = 0
Vin = 7.65
1 1 0 0
Successive Approximation ADC Example
• MSB LSB• Average high/low limits• Compare to Vin
• Vin > Average MSB = 1
• Vin < Average MSB = 0
• Bit 3• (8.125+7.5)/2 = 7.8125• 7.65 < 7.8125 Bit 3 = 0
Vin = 7.65
1 1 0 0 0
Successive Approximation ADC Example
• MSB LSB• Average high/low limits• Compare to Vin
• Vin > Average MSB = 1
• Vin < Average MSB = 0
• Bit 2• (7.8125+7.5)/2 = 7.65625• 7.65 < 7.65625 Bit 2 = 0
Vin = 7.65
1 1 0 0 0 0
Successive Approximation ADC Example
• MSB LSB• Average high/low limits• Compare to Vin
• Vin > Average MSB = 1
• Vin < Average MSB = 0
• Bit 1• (7.65625+7.5)/2 = 7.578125• 7.65 > 7.578125 Bit 1 = 1
Vin = 7.65
1 1 0 0 0 0 1
Successive Approximation ADC Example
• MSB LSB• Average high/low limits• Compare to Vin
• Vin > Average MSB = 1
• Vin < Average MSB = 0
• Bit 0• (7.65625+7.578125)/2 =
7.6171875• 7.65 > 7.6171875 Bit 0 = 1
Vin = 7.65
1 1 0 0 0 0 1 1
Successive Approximation ADC Example
• 110000112 = 19510
• 8-bits, 28 = 256• Digital Output
• 195/256 = 0.76171875• Analog Input
• 7.65/10 = 0.765
• Resolution• (Vmax – Vmin)/2n 10/256 = 0.039
1 1 0 0 0 0 1 1
7 6 5 4 3 2 1 00
0.2
0.4
0.6
0.8
1
Volta
ge
Bit
Vin = 7.65
Successive-approximation ADC
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
D2 D1 D0
0.000V
0.625V
1.250V
1.875V
2.500V
3.125V
3.750V
4.375V
Vref: 5V Vin= 3.4V
clock cycle 2D1 = 0[Vin < Vappr]
clock cycle 3D0 = 1[Vin > Vappr]
full scale value
clock cycle 1D2 = 1[Vin > Vappr]
Vappr
Binary search for a 3-bit ADC
3.4 > (5 + 0)/2 = 2.5 Bit 2 = 13.4 < (5 + 2.5)/2 = 3.75 Bit 1 = 03.4 > (3.75 + 2.5)/2 = 3.125 Bit 0 = 1
Counter Ramp Converter • Counter-ramp converters comprise a D-A converter, a single
comparator, a counter, a clock and control logic • When a conversion is required a signal (conversion request) is
sent to the converter and the counter is reset to zero. • The purpose of the sample-and-hold amplifier is to freeze the
analogue voltage at the instant the HOLD command is issued and make that analogue voltage available for an extended period.
• A clock signal increments the counter until the reference voltage generated by the D/A converter is greater than the analogue input At this point in time the output of the comparator goes to a logic 1, which notifies the control logic the conversion has finished encoder input signal digital output
• The value of the counter is output as the digital value. • The time between the start and end of the conversion is known
as the conversion time. • A drawback of the counter-ramp converter is the length of time
required to convert large voltages. A 10 bit a/d converter will require 1024 iterations to resolve the maximum input voltage.
• The worst case must be assumed when calculating conversion times
Counter Ramp Converter
Integrating ADC
Speed: Low Cost: Low Accuracy: High
References:www.ti.com/lit/an/slaa587/slaa587.pdf1. Understanding Data Converters – SLAA0132. ADS8318 data sheet – SLAS568Ahttp://www.analog.com/static/imported-files/tutorials/MT-003.pdfhttp://www.hit.bme.hu/~papay/edu/Acrobat/DataConv.pdfEvaluating High Speed DAC Performance by Walt Kester – Analog Devices MT-013 Tutorial http://www.ni.com/white-paper/4806/en/Home > Products and Services > White Papers > Understanding Resolution in High-Speed Digitizers/Oscilloscopeshttp://inst.eecs.berkeley.edu/~ee247/fa10/files07/lectures/L11_2_f10.pdfhttp://194.81.104.27/~brian/DSP/ADC_notes.pdfume.gatech.edu/mechatronics_course/ADC_F10.pptx