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A Random Access Scan A Random Access Scan Architecture to Reduce Hardware Architecture to Reduce Hardware

OverheadOverheadAnand S. Mudlapur

Vishwani D. AgrawalAdit D. Singh

Dept. of Electrical EngineeringAuburn University, AL – 36849 USA

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Motivation for This Work• Serial scan (SS) test sequence lengths

and power consumption are increasing rapidly.– Reduction of test power and test time are

complimentary objectives in serial scan.• Scope of increasing delay fault coverage

is limited in serial scan. • In spite of the three advantages (test

time, power, and delay fault coverage) random access scan (RAS) is not popular due to high overhead.

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Outline• Introduction• Review of our “toggle” Flip-Flop

design• Highlight the uniqueness and

feasibility of our design due to the reduction of two global signals

• Results on ISCAS Benchmark Circuits• Conclusion

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Introduction• Random Access Scan (RAS) offers a single

solution to the problems faced by serial scan (SS):– Each RAS cell is uniquely addressable for read

and write.– RAS reduces test application time and test power

which are otherwise complimentary objectives.• Previous and current publications on RAS:

• Ando, COMPCON-80• Wagner, COMPCON-83• Ito, DAC-90• Baik et al., VLSI Design-04, ITC-05, ATS-05, VLSI Design-06• Mudlapur et al., VDAT-05

• Disadvantage: High routing overhead – test control, address and scan-in signals must be routed to all flip-flops.

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Contributions of Present Work

• Eliminate scan-in signal from circuit by using a toggling RAS flip-flop.

• Eliminate routing of test control signal to flip-flops.

• Provide a new scan-out architecture:– A hierarchical scan-out bus– An option of multi-cycle scan-out

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Serial Scan (SS)

Example: Consider a circuit with 5,000 FFs and 10,000 combinational test vectors

Total test cycles = 5,000 x 10,000 + 10,000 + 5,000

= 50,015,00050,015,000

Combinational Circuit

FFFFFFScan-inScan-in Scan-outScan-out

PIPI POPO

Test controlTest control(TC)(TC)

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Random Access Scan (RAS)

During every test, only a subset of all Flip-flops needs to be set and observed for

targeted faults

Combinational Circuit

FFFFFF

PIPI POPO

Scan-outScan-out busbus

Decoder

Address Address InputsInputs

Scan-inScan-inTCTC

These signals are eliminated in our design

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The “Toggle” RAS Flip-Flop

M S

ClockClock

MUXCombinational Combinational

Logic DataLogic Data

Row Decoder Column Decoder

Combinational Combinational Logic Logic

To Output To Output BUSBUS

Address (logAddress (log22nnffff))

yyxx

√√nnff ff LinesLines √√nnff ff LinesLines

RAS-FFRAS-FF

0

1

Output Output BUSBUS

ControlControl

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Toggle Flip-Flop Operation

Function ClockAddress decoder

outputs

Row (x) Column (y)

Normal Data Active 0 0

Toggle Data

Inactive 1 Active Clock

Inactive Active Clock 1

Hold DataInactive 1 0Inactive 0 1Inactive 0 0

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Toggle Flip-Flop Operation (contd.)

RASFF0

RASFF1

RASFF1

Unaddressed FFsUnaddressed FFsAddressed FFAddressed FF

RASFF0

Deco

ded

addr

ess

lines

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Macro Level Idea of Signals to RAS-FF

x1x1

x2x2

x3x3

x4x4

y1y1 y2y2 y3y3 y4y4

RASFF11

RASFF14

RASFF12

RASFF13

RASFF11

RASFF14

RASFF12

RASFF13

RASFF21

RASFF24

RASFF22

RASFF23

RASFF31

RASFF32

RASFF33

RASFF34

RASFF41

RASFF42

RASFF43

RASFF44 To Next

Level

}

From 3 Other RAS

ClustersRASFF22

4-to-1 Scan-out

Macrocell

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Scan-out Macrocell

• A 4x4 block scan-out data flow and control logic

• Two D-FFs may be inserted at the outputs of macrocell for multi-cycle scan-out.

To Next LevelTo Next LevelOutput BUSOutput BUS

Control Signal toControl Signal toNext Level BUSNext Level BUS

Data Bus FromData Bus From4 RAS FFs4 RAS FFs

{Control FromControl From4 RAS FFs4 RAS FFs

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Routing of Decoder Signals in RAS

COLUMN DECODER

ROW

DECODER

Flip-FlopsPlaced on a Grid Structure

Address Address (log(log2 2 √√ nnffff))

Address Address (log(log2 2 √√ nnffff))

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Gate Area Overhead

%nnn

ffg

ff10010

4

%nn

nn

ffg

ffff100

10

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Gate area overhead of Gate area overhead of Serial ScanSerial Scan ==

Gate area overhead of Gate area overhead of Random Access ScanRandom Access Scan==

wherewhere n nff ff – Number of Flip-Flops– Number of Flip-Flopsnng g – Number of Gates– Number of Gates

Assumption: D-FF contains 10 logic gates.

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Gate Area Overhead (Examples)

1. A circuit with 100,000 gates and 5,000 FFsGate overhead of serial scan = 13.3 %

Gate overhead of RAS = 20.0 %

2. A circuit with 500,000 gates and 5,000 FFsGate overhead of serial scan = 3.6 %

Gate overhead of RAS = 5.5 %

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Overhead in Terms of Transistors

%nnn

fft

ff 10028

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Gate area overhead of Gate area overhead of

Serial ScanSerial Scan ==

%nnn

fft

ff 10028

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Gate area overhead of Gate area overhead of

Random Access ScanRandom Access Scan==

Synthesis performed on SUN ULTRA 5 MachineSynthesis performed on SUN ULTRA 5 MachineRAS has 16 transistors more than SS Flip-FlopRAS has 16 transistors more than SS Flip-Flop

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Test Time

0

200

400

600

800

Test

clock

cycle

s (th

ousa

nds)

s3271 s3384 s5378 s13207Circuits

Test cycle reduction

Scan RAS

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Test Power

0.001

0.01

0.1

1

Test

Pow

er

(Nor

mal

ized

to

seria

l sca

n)

s3271 s3384 s5378 s13207Circuits

Scan RAS

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Case Study on an Industrial Circuit

• A case study on an industry circuit was performed at Texas Instruments India Pvt. Ltd.

• The preliminary results were as follows:1. The gate area overhead of RAS for a chip with

~5500 Flip-Flops and ~100,000 NAND equivalent gates was of the order of 18 %

2. 75 % reduction in test time was observed. A speed-up of up to 10X could be achieved using special heuristics

3. An approximate estimate of the routing and area overhead of RAS after physical layout was estimated as 10.4 %

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Conclusion• New design of a “Toggle” Flip-Flop

reduces the RAS routing overhead.• Proposed RAS architecture with new FF

has several other advantages:– Algorithmic minimization reduces test

cycles by 60%.– Power dissipation during test is reduced by

99%.• A novel RAS scan-out method presented.• For details on “Toggle” Flip-Flop, see

Mudlapur et al., VDAT-05.