Post on 11-Feb-2016
description
A CPU MODULE FOR A SPACECRAFT CONTROLLER WITH HIGH THROUGHPUT
SPACEWIRE INTERFACES
International SpaceWire Conference 20084th-6th November 2008 Nara, JapanNara Prefectural New Public Hall
○Toru Sasaki, Minoru Nakamura, Tadashi Yoshimoto, Minoru Yoshida, Shoji Yoshikawa
MITSUBISHI ELECTRIC CORPORATIONADVANCED TECHNOLOGY R&D CENTER
Spacecraft Controller
Table of Contents
1. Introduction2. CPU module3. DMA Controller 4. Evaluation5. Conclusion
DMAController
SpaceWireController
PCI busController
IP
IP
FPGA
Evaluation
Melco standard small satellite
CPU module
IntroductionPayloadMelco Standard Small Satellite SyMelco Standard Small Satellite Sy
stem stem (200kg-class)
Concepts○ Low Cost, Short Term Integration, Mission Flexibility
Missions○ Science, Deep Space○ Earth Observation- high performance mission
Star Tracker
Gyro
GPSReaction Wheel
IntegratedPower Controller Unit
Battery
Thruster
Sun Sensor
Solar Array Paddle
Sensor/Actuator
Power Supply
Communication Equip.
EO SAR Sensor
Payload
Solar Array Paddle
SIGINTELINT
Open ArchitectureSCU
Science
CPU module with high throughput SpaceWire
CPU module
Spacecraft Controller
FPGA Function○Various IPs-Interrupt Controller, DMA Controller, SpaceWire Controller
Components
CPU module
CPU module
※ DMA : Direct Memory Access : DMA data path
CPUHR5000(JAXA)
core 100MHz bus 50MHz
FPGA RTAX2000TM(Actel)
Bus PCI 32bit 33MHz
SystemMemory
2MB with ECC
SpaceWire 2 ch
CPU module function○ DH (Data Handling)○ AOC (Attitude and Orbit Control)○ SM (Satellite Management)
PCI
FPGA
SystemMemory
CPU module
SpaceWire
CPU
PCI BusBridge
Controller
InterruptController
SerialInterfaceCotroller
WatchDogTimer
SpaceWireController
DMAController
Timer GPIOPCI BUS
33MHzClock
50MHzClock
FPGAHR5000
・・・
FPGA functiondiagram
DMAController
InterruptController
WatchDog Timer GPIO
SpWControllerSerial I/F
Controller
PCI BusBridge
Controller
50MHzClock
33MHzClock
PCI BusBridge
Controller
InterruptController
SerialInterfaceCotroller
WatchDogTimer
SpaceWireController
DMAController
Timer GPIOPCI BUS
33MHzClock
50MHzClock
FPGAHR5000
・・・FPGA functiondiagram
DMAController
InterruptController
WatchDog Timer GPIO
SpWControllerSerial I/F
Controller
PCI BusBridge
Controller
50MHzClock
33MHzClock
CHARACTERISTICS of DMA Controller
○ 8 channels - 4 channels for sending 4 channels for receiving○ Burst transfer mode - 2, 4 and 8 words (1 word = 4 bytes)○ Double Register Mode→ Next slide
DMA Controller Feature
※EOP: End of SpaceWire Packet
PCI busBridge
Controller
DMA Controller
・・・
InterruptController
ControllAddress
Data
Internal Bus
・・・
DATA
・・・AddressDecoder CH0
StateController
CH1
CH7Data PathContoller
DATA
DATAEOP Signal
B registersA registers
0ch BufferController
8 wordBuffer
From SpaceWire Controller
DATA
EOPSIGNAL
Data PathController
CH0
CH1
CH7
AddressDecoder
Double Register Mode
Control RegisterControl Register Address RegisterAddress Register
Count RegisterCount Register
Control RegisterControl Register Address RegisterAddress Register
Count RegisterCount Register
B set
A setDouble Register Mode
○ 2 sets of registers
-You can set another set of registers even while DMA controller is transferring data.
○ A/B change by DMA completion or EOP
- Automatic change- Separate management of SpaceWire packets A B
DMA active waiting
BADMA activewaiting
A BDMA active waiting
expiration of A count registeror EOP arrival
expiration of B count registeror EOP arrival
expiration of A count registeror EOP arrival
Evaluation
Condition○Loop back wiring○Link Speed = 10Mbps○Lowered CPU Performance (~1MIPS) to emphasize the effect
SpaceWire
TX
RX
SendData
ReceiveData
CPU(1MIPS) FPGA
SRAM
CPU module
Loop BackMeasurement item1. Transfer rate [Mbps]- Data Size[KB] / Time[ms]×10-6
2. Comparison- Double Register Mode VS Single Register Mode - At various size of SpW packet
Purpose○Test the efficiency of Double Register Mode
send and receive2000 SpW packets
※burstlength = 8
0123456789
0 200 400 600 800
Result
length of SpW packet [bytes]
Results1. Transfer rate • 7.5 Mbps (max)• 93% of full performance2. Comparison • Double/Single = 1.5• Less effective at short packet
S/W setup time < DMA transfer time
start A start B
DMA transfertime for A reg
DMA transfertime for B reg
start A
start A start B
DMA transfertime for A reg
start A
Time
TimeDMA transfer
timer for A regDMA transfertime for B reg
DMAC
S/W
S/W
DMAC
long SpW packet
short SpW packetS/W setup time > DMA transfer time
GOOD Performance!
Poor performance!
We want to make the SpaceWire link speed faster .
setup time
setup time
Wait Wait
Transfer Rate [Mbps] Double Register Mode
Single Register Mode
1.5 times
Conclusion
○ Melco has developed a CPU module with SpaceWire.
○ The DMA Controller enhanced the efficiency of SpaceWire with Double Register Mode.
○ Evaluation of Double Register Mode - 7.5 Mbps (max.) @ 10Mbps link, - 93% of full performance@1MIPS CPU - 1.5 times faster than Single Register Mode
○ We have a plan to raise SpaceWire link speed and search the performance limit.
Thank you for your attention
Thank you for your attention