A Comparison Between Sub-threshold and Adiabatic Power

Saving Techniques

By Jonathan Bolus and

Stuart Wooters

Carry Look Ahead Adder

Power Comparison of different VDD

Power Consumption Comparison with VDD=1

Sub-threshold Summary

Energy Consumption: 7.18 fJ/addition f = 20 MHz Power Consumption: 143.6 nW Number of Devices: 1230

ECRL Efficient Charge Recovery Logic

Essentially Differential Cascode Voltage Switch Logic (DCVSL).

VDD replaced by power clock:

Clock Timing

ECRL Inverters

Power Consumption

Adiabatic Adder Summary

Energy Consumption: 300 fJ/addition f = 20 MHz Power Consumption: 6 uW Number of Devices: 1208

Conclusions

Adiabatic is not as affective at small values of VDD (lower than 2V). This is evident in the 90nm technology we used.

Sub-threshold saved 26x the power compared to VDD=1

References

A 0.5V, 400MHz, V/sub 00/-hopping processor with zero-V/sub TH/ FD-SOI technologyKawaguchi, H.; Kanda, K.; Nose, K.; Hattori, S.; Dwi, D.; Antono, D.; Yamada, D.; Miyazaki, T.; Inagaki, K.; Hiramoto, T.; Sakurai, T.;Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International2003 Page(s):106 - 481 vol.1 Digital Object Identifier 10.1109/ISSCC.2003.1234227

An Efficient Charge Recovery Logic CircuitYong Moon, and Deog-Kyoon Jeong;IE Journal of Solid-State Circuits, Vol, 31, No.4, April 1996