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A 5.2 GHz BFSK Receiver with On-Chip Antenna
for Self-Powered RFID Tags and Medical Sensors
Peter H. R. Popplewell, Victor Karam, Atif Shamim, John Rogers, and Calvin Plett
Department of Electronics, Carleton University, 1125 Colonel By Drive, Ottawa, Ontario, Canada, K1S 5B6Email: ppopp@doe.carleton.ca
Abstract— A completely integrated receiver design suitablefor short range wireless applications is presented. The circuitrepresents one half of an SoC solution that makes use of anon-chip antenna, and consumes 5.5 mW while receiving. A thinfilm ultracapacitor and a solar cell can be stacked on top of the chip to supply power to the radio; yielding a completelyintegrated solution. The receiver makes use of a PLL toinitially lock an RF VCO which is then allowed to be injection-locked to an incoming FM signal. An integrated antennaprovides adequate gain given the short range radio’s intendedapplications. The solution has a communication range of 1.75 m
which can be increased at the expense of the bit-rate, increasedpower consumption in the receiver, or by using off-chip antennas.
Index Terms - Injection Locked Oscillator, Integrated Antenna,Medical Sensor Readout, RFID, Self Powered Circuit.
I. INTRODUCTION
The increasing adoption of RFID technologies by merchant
corporations has fuelled much research into new, more power
efficient, size efficient, and ultimately more cost efficient
methods of radio communication. Applications for RFID tags
include asset tracking and merchandize scanning where a low
communication range is acceptable, but the cost of a particular
solution directly dictates its success. A completely integrated
and self-powered SoC solution is small and cost effective,precluding the need for off-chip components such as passives,
a battery, and an antenna which increase the system size and
cost considerably.
Surprisingly, the requirements for an RF device that can
communicate the data from medical sensors can best be met by
a device that is similar to an RFID tag, although the cost of the
solution may be somewhat less important. In the treatment of
cancer patients by means of radiation, dosimeters are used to
measure the dose of radiation experienced at different locations
on the body. Current generation dosimeters are wired and
can be both cumbersome and detrimental to the treatment
process as the metal in the wire can block the radiation. As
such, a short range radio for transmitting the output data fromthe sensor would be beneficial. Unfortunately, most wireless
devices require batteries which typically contain elements of
high atomic mass number and would scatter radiation. Thus,
having a self-powered solution with no battery is critical for
this application.
The receiver presented in this paper represents one half
of a completely integrated SoC solution which is fabricated
in a 0.13 µm CMOS process on a standard, low resistiv-
ity silicon substrate. The solution makes use of an on-chip
antenna, and can be powered by an ultracapacitor and solar
cell which are fabricated on top of the chip. If the receiver
is always on and searching for an incoming signal (allowing
a transmitter to transmit efficiently), it consumes 5.5 mW of
power. Conversely, if the receiver is communicating with a
transmitter that is always on then the receiver can be enabled
only intermittently, dropping its average power consumption
considerably.
I I . ON-C HI P ANTENNA DESIGN
The use of an on-chip antenna allows for a very compact and
cost efficient short range communication solution. Previous
studies, [1], [2], have demonstrated successful use of inductive
integrated antennas, but these antennas typically rely on high
resistivity substrates. Here we use an inductive design which
is fabricated on the same low resistance silicon substrate as
the receiver’s circuits. The antenna is a rectangular single turn
loop with an outer diameter of 825 µm by 675 µm, a metal
width of 100 µm, a feeding gap of 100 µm, and having room
for the active circuitry of the receiver to be placed in the center.
A square loop is typically not the best choice for an on-chip
inductor because it has sharp 90o bends which increase the
series resistance of the structure and therefore decrease the Qwhen compared to an octagonal geometry, yet the sharp bends
in the square loop tend to increase the radiation resistance and
consequently the gain of the antenna. The peak gain of the
antenna was measured in an anechoic chamber to be -22 dBi.
The measured input impedance of the antenna is Z in = 9.6 +
j 58.0 Ω at 5.2 GHz, corresponding to an inductance of 1.8
nH with a Q of 6.
III. RECEIVER DESIGN
A. Overall Topology
The receiver topology is based on a traditional 3rd order PLL
with a static divide ratio and a second order on-chip loop filter.
Unique to the design is that the loop can be opened and closedto allow the VCO to be injection-locked by the incoming FM
signal, while the divider, phase-frequency detector (PFD), and
a second charge pump (CP) work together to demodulate the
baseband signal. The basic topology is shown in Fig. 1.
The receiver loop is initially closed to set the center
frequency of the oscillator to 5.2 GHz, which is 64 times
the 81.25 MHz reference. The loop is then opened, and the
oscillator is injection-locked to the incoming FM modulated
signal being broadcast by the transmitter. The on-chip antenna
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Fig. 1. Receiver topology.
is impedance matched to the input of a low noise amplifier
(LNA), which has a gain of 20 dB, and couples the FM
modulated input into the spectrum of the initially free-running
oscillator. If the coupled signal is strong enough and if the
instantaneous frequency of the FM input is always within the
locking bandwidth of the oscillator, the oscillator is injection-
locked to the incoming signal.
B. Adler’s Equation for Locking Bandwidth
The amplitude of an injected signal required to injection-
lock an oscillator was analyzed and quantified by [3], and
the topic was recently re-visited by [4]. Assuming that the
amplitude of the injected voltage (V inj) is much smaller than
the amplitude of the free-running oscillator (V osc), the locking
range can be approximated by
ωL ≈ω0
2QU
V injV osc
(1)
where QU is the quality factor of the oscillator’s unloaded
tank circuit, ω0 is the center frequency of the free-running
oscillator, and ωL is the single sided locking bandwidth, i.e.,
the oscillator can be locked from ω0 − ωL to ω0 + ωL.
C. Receiver Sensitivity
The oscillator has a free-running differential peak to peak
swing of 1.0 V and a tank inductor with Q = 5. The Q of the
VCO’s tank circuit is purposely reduced, by adding parallel
resistors, in order to increase the injection-locking bandwidth
defined by (1). The receiver is required to process a BFSK
input signal that switches between 5.1995 GHz and 5.2005
GHz, requiring a one sided locking bandwidth of greater than
500 kHz from the receiver’s VCO. Working backwards from
(1), an injected signal of V inj = 1.16 mV results in a one
sided locking bandwidth of over 600 kHz. As the LNA circuit
has a voltage gain of greater than 20 dB, this corresponds to
a minimum required signal of 116 µV from the conjugately
matched antenna.
D. Coupled LNA and VCO Design
At the heart of the receiver is the coupled LNA/VCO
circuit shown in Fig. 2. The differential input to the LNA
is conjugately matched to the differential output impedance of
the antenna, i.e., 9.6 + j 58.0 Ω. The output of the LNA is
lightly coupled to the tank of the complimentary cross coupled
Fig. 2. Coupled LNA/VCO circuit.
VCO circuit using capacitors that are small relative to that
of the varactors in the VCO so as not to disturb the tank
resonance. A programmable tail current in the VCO helps to
limit the peak to peak output swing of the VCO to only 1
V such that the VCO can be injection-locked based on thecalculations of section III-C.
IV. COMMUNICATION RANGE AND THE FRIIS EQUATION
In order to quantify the system’s theoretical communication
range, an analysis must be performed that takes into account
the gain of the transmitter and receiver antennas, the power
at the terminals of the transmitter antenna (P T ), and the
free space losses to predict the power at the terminals of
the receiver’s antenna (P R). The maximum communication
range is determined by the sensitivity of the receiver. The
Friis equation [5] is traditionally used for this budgeting
purpose. The Friis equation, assuming a conjugate match toboth antennas, can be written as
P R = P T GT GR
λ0
4πr
2(2)
where GT and GR are the gains of the transmit and receive
antennas respectively, λ0 is the signal’s wavelength in free
space (λ0 ≈ 57.7 mm at 5.2 GHz), and r is the distance
between the two antennas. A typical communication system
could have one transceiver making use of the on-chip antenna
with a gain of -22 dBi while communicating with another
transceiver which uses a 6.7 dBi patch antenna. Knowing
the power at the terminals of the transmitting antenna, andrecalling the required signal at the terminals of the receiver’s
antenna, one can work backwards from (2) and determine that
a communication range of 1.75 m is possible. Similarly, if
on-chip antennas are used with both transceivers the range
decreases to 6.5 cm. Fig. 3 shows the test setup that was used
in an anechoic chamber to verify the system’s communication
range. Fig. 4 summarizes the communication ranges that are
possible using two on-chip antennas, or using one on-chip
antenna communicating with a patch antenna.
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Fig. 3. Communication range measurement made in an anechoic chamber.
Fig. 4. Communication range vs. antenna configurations.
V. MEASURED RESULTS
Recall from section III-A that the receiver’s PLL serves to
pre-tune the VCO to 5.2 GHz before the loop is opened and
the VCO is able to injection-lock to the incoming FM signal.
An important aspect of the design is that the control voltage
of the VCO remain constant during open loop operation
or the VCO will drift from 5.2 GHz and injection-locking
will be impossible. There are three aspects to the designwhich maintain the control voltage long enough to enable
the reception of data, namely the use of a unity gain loop
buffer, the loop switch design, and the primary CP design.
The loop buffer serves to prevent the bleeding off of charge
on the loop filter during open loop operation through the
VCO’s varactors. Having unity gain is important such that the
characteristics of the loop are not altered. The loop switch
is a standard CMOS transmission gate with dummies that
prevent channel charge from the switch’s transistors from
altering the charge held on the loop filter at the moment the
loop is opened. Due to the switch’s finite impedance, the
primary CP is disabled when the loop is opened to further
prevent charge on the loop filter from bleeding off throughthe CP. Once the VCO is injection-locked, the rest of the loop
components in the receiver, namely the divider, PFD, and the
secondary CP attempt to compensate for the now modulated
VCO by producing a voltage signal that, if connected to the
VCO, would counter its frequency/phase change. Note that by
switching the up/down connections between the PFD and the
secondary CP the output bitstream is now equal in phase to
the original data. Fig. 5 shows the spectrum of the VCO while
injection-locked to the BFSK input signal and Fig. 6 shows
the input bits to the BFSK modulated source and the measured
output bits from the receiver for a bit-rate of 1 kb/s. The noise
on the receiver’s baseband output results from cycle slips at
the PFD inputs which occur at the beat frequency between the
reference signal and the divider output. Interestingly, this beat
frequency is also what determines the maximum bit-rate the
receiver can tolerate.
Fig. 5. VCO injection-locked to BFSK input.
Fig. 6. Measured bitstream out of the receiver.
A. Tradeoffs Between Power, Range, and Bit-Rate
When there is a frequency shift of the injection-locked VCO
signal, corresponding to a transition in the bitstream, the time
required for the receiver loop to demodulate is dependent on
the phases of the inputs to the PFD, namely the reference
(F REF ) and the divider output (F DIV ). In open-loop demodu-
lation, the PFD will behave as a frequency detector/comparator
because F DIV is either higher (representing a logic high) or
lower (representing a logic low) than F REF . The solid line
in Fig. 7 illustrates the PFD’s behavior seen at the output of the CP for the case when F REF > F DIV . The initial phase
difference is assumed to start at point A. The phase difference
(θREF − θDIV ) increases with time, passing through points
B and C until the phase difference equals 2π (or multiples
thereof) where a cycle slip occurs because the phases of F REF and F DIV are aligned (point D). This pattern repeats without
bound towards point Z.
If there is a transition in the bitstream, then F REF < F DIV and the time required for the CP to begin reversing the
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Fig. 7. CP output vs. phase difference at PFD.
direction of current flow through the loop filter depends on the
phase difference at the PFD inputs. If the transition happens
when the phase difference is 0 radians (or multiples of 2π),
indicated by point A (or point D), then there is no delay before
the CP begins reversing current. If, however, the transition
happens when the phase difference is slightly lower than 2π(point C), then the phase difference would begin decreasing,
passing through point B and onto point A where the CP finally
begins reversing the current. The worst case delay until the
current reverses occurs when the phase difference is slightly
lower than 2π at the time of a bit change, and the length of thedelay is inversely related to the beat frequency between F REF and F DIV . The period of this beat frequency is also the time
between cycle slips. Here we have used a reference frequency
of 81.25 MHz in the receiver, a bit-rate of only 1 kb/s, and a
∆f = 500 kHz. These settings were chosen such that the
maximum delay between a bit change (and corresponding
frequency change) at the input to the PFD in the receiver and
the resulting bit change at the output of the receiver’s CP is
≈ 12 % of the bit length. The beat period at the input of the
PFD is given by
T BEAT =1
∆f /N =
1
500 kHz/64= 128 µs (3)
Increasing ∆f would clearly decrease this wait time, but as (1)
suggests, this would require greater received power to keep the
receiving VCO injection-locked. Recalling (2) we see that P Rcan be increased with a decrease in range, or increased antenna
gain. Thus there are many trade-offs that can be made.
A microphotograph of the receiver is shown in Fig. 8.
V I . ULTRACAPACITORS AS A POWER SOURCE
Developments in the design and manufacturing of ultra-
capacitors have made it possible to meet the power supply
requirements of small integrated circuits without using a
battery. Typical 100 µm thick nanostructured electrode devices
can give up to 1 F/cm2 [6], [7], which is ample charge storageto power the circuits discussed in this paper. A complete
transceiver chip measuring 2 mm by 2 mm, of which the
integrated antenna and the circuitry occupy one quarter, allows
for three 1 mm by 1 mm ultracapacitors to be manufactured
on top of the remaining three quadrants of the chip without
covering up the antenna which would decrease its gain. This
results in a 30 mF capacitance which is capable of ≈ 4.2 µAhr
or ≈ 5 mA for three one second bursts between chargings.
Standard integrated capacitors are fabricated in the regular
Fig. 8. Receiver test chip microphotograph.
CMOS process below the ultracapacitors and serve as local
charge storage devices because they can deliver charge quicker
than the ultracapacitors which recharge them. Finally, a solar
cell can be manufactured on top of the ultracapacitors to trickle
charge the ultracapacitors using ambient light.
VII. CONCLUSION
A completely integrated 5.2 GHz BFSK receiver with an
on-chip antenna has been presented. If the receiver is always
on, the measured power consumption is 5.5 mW, enabling
the corresponding transmitter to power up only intermittently
and to save power. The communication range is 1.75 m when
one transceiver uses an on-chip antenna to communicate withanother transceiver using a patch antenna. The receiver uses a
PLL to pre-tune a VCO, and the loop is then opened to allow
the VCO to be injection-locked to the incoming FM signal.
The remaining loop components serve to demodulate the
signal. The architecture is well suited for use in inexpensive
RFID tags, and wireless radiation sensors where solutions with
no battery (that would scatter radiation) are desirable.
REFERENCES
[1] R. N. Simons, D. G. Hall and F. A. Miranda, “RF telemetry system for animplantable bio-MEMS sensor,” in IEEE MTT-S International MicrowaveSymposium Digest , June, 2004, pp. 1433–1436.
[2] R. N. Simons, D. G. Hall and F. A. Miranda, “Spiral chip implantable
radiator and printed loop external receptor for RF telemetry in bio-sensorsystems,” in Proceedings of the IEEE Radio and Wireless Conference,September, 2004, pp. 203–206.
[3] R. Adler, “A study of locking phenomena in oscillators,” Proceedings of the IRE , vol. 34, pp. 351–358, June, 1946.
[4] B. Razavi, “A study of injection locking in oscillators,” IEEE Journal of Solid State Circuits, vol. 39, no. 9, pp. 1415–1424, September, 2004.
[5] H. T. Friis, “A note on a simple transmission formula,” in Proceedingsof the IRE , May, 1946, pp. 254–256.
[6] A. Burke, “Ultracapacitors: why, how, and where is the technology,” Journal of Power Sources, vol. 91, pp. 37–50, 2000.
[7] R. Kotz and M. Carlen, “Principles and applications of electrochemicalcapacitors,” Electrochimica, vol. 45, pp. 2483–2498, 2000.
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