Post on 14-Dec-2015
A 10b Ternary SAR (TSAR) ADC with Decision Time Quantization
Based Redundancy
Jon Guerber, Manideep Gande, Hariprasath Venkatram,
Allen Waters, Un-Ku Moon
Oregon State University, Corvallis OR USA
TSAR Outline
• SAR Motivation
• TSAR Structure and Benefits
• Implementation
• Measured Results
• Conclusions
2
SAR Motivation
• SAR Contributions– Low Power– Scalable– Good Small
Process Node FOM– Little/No Static
Current
• High Efficiency SAR Design Factors– Power: Cap array, comparator, DAC drivers, logic– Speed: Comparator delay, reference settling– Resolution: Settling errors, cap mismatch
SAR
DAC Driver
DAC Driver
Cap DAC
Cap DAC
VIN
DOUT
3
Merged Capacitor Switching SAR
• Merged Capacitor Switching (MCS) – Sampling reference
is Vcm
– Differentially switches DAC
– Minimizes switching power
– Maintains virtual node common mode
[Hariprasath ELetters 2010]
C2^(N-3)C2^(N-2)C
VINP
SAR
DACP
VT
DACN
VINN
C2^(N-3)C2^(N-2)C
VCM
VCMVDD
VDD
4
Comparator Delay Variation per Stage
Comparator Transfer Function
tOUT GV = V exp A - 1 t / τ
Comparator Delay vs. Stage Voltage
• Comparator decision time increases linearly with stage
5
TSAR Outline
• SAR Motivation• TSAR Structure and Benefits
– Redundancy, Speed, and Power– Residue Shaping– Stage Grouping
• Implementation• Measured Results• Conclusions
6
Ternary SAR (TSAR) Architecture
• Ternary SAR (TSAR) uses comparator delay information to create a coarse third level– Middle level is based on input magnitude– DAC operation is skipped for a middle code
Vfs/4
-Vfs/4
Vfs
-Vfs
10
01
00
Subtract Vfs/2 From
Input
Add Vfs/2 to Input
Defer Decision to Next Stage
Digital Output
DAC Action
Time Comp = 1
Voltage Comp = 1
Voltage Comp = 0
Time Comp = 0
7
SAR
DAC Driver
DAC Driver
Cap DAC
Cap DAC
VIN
DOUTTime Comp
Delay
TSAR Redundancy
• TSAR Provides 1.5b/stage redundancy– Tolerates small settling errors, fixes over-range errors– No extra cycles or sub-radix arrays needed– Adds just like conventional 1.5b/stage pipelined ADCs
Vfs/4
-Vfs/4
Vfs
-Vfs
10
01
00
Subtract Vfs/2 From
Input
Add Vfs/2 to Input
Defer Decision to Next Stage
Digital Output
DAC Action
Time Comp = 1
Voltage Comp = 1
Voltage Comp = 0
Time Comp = 0
X XX X
X XX X
d1
d2
d3
d4
b1 b2 b3 b4 b5
8
TSAR Speed Enhancements
• Comparison Time Reduced in Coarse Steps– Codes that take longer then Vfs/4 = middle code– Comparator delay per stage is now reduced– Worst case conversion delay shortened
9
Binary SAR
TSAR
Fixed Conversion Time
TSAR DAC Activity Reduction
• TSAR Switching Activity Reduction– When the input is in the center code, no DAC cap is
switched– Like “Multi-Comparator” Circuit but with no extra
voltage comparators [Liu, VLSI 2010] 10
Switch
Switch
Switch
Stage 1 Stage 2 Stage 3
No Switching
VREF
-VREF
0
Switch
TSAR Residue Shaping
• TSAR Residue Shaping due to 1.5b redundancy– Improves SQNR by 6dB (Reduces DAC spread by ½)– Further reduces latter stage DAC activity
1 -11/2 -1/2
1/2
0
Stage 1
1/4 -1/4
1 -11/2 -1/2
1/2
0
Stage 2
1/4 -1/4
3/2
1 -11/2 -1/2
1/2
0
Stage 3
1/4 -1/4
7/2
11
-1/512 1/512-1/1024 1/10240
.05%.05%
99.9% of CodesStage 9 PDF
TSAR Stage Grouping and Skipping
• TSAR Stage Grouping– Allows for cycle skipping (10b in 8.02 ave. cycles)– Reduces number of distinct reference levels
VFS
-VFS
VFS
-VFS
VFS VFS VFS
-VFS -VFS -VFS
VIN
STAGE: 1 2 3 4 5
Skip
Stage
Don’t
Charge
Caps
ACTION: Normal
Operation
Normal
Operation
Normal
Operation
12
TSAR Stage Grouping and Skipping
• TSAR Stage Grouping– Grouping based on
power simulations– Comparator power
also reduces (20% less on average)
1 2 3 4 5 6 7 8 9Stages:
Delay Reference(As a fraction of Vfs) 1/8 1/10241/32
Comparisons Per Code
13
TSAR Switching and Driver Energy
• TSAR Energy Reductions over the MCS SAR– Average DAC switching energy is reduced by 63.9%– Average driver energy is reduced by 61.3%
DAC Switching Energy per Code Driver Energy per Code
14
TSAR Outline
• SAR Motivation• TSAR Structure and Benefits
• Implementation– Comparator and Logic Modifications– Calibration– Layout
• Measured Results• Conclusions
15
TSAR Implementation
• TSAR Implemented in 0.13µm CMOS – Delay elements consist of current starved inverters– Input switches are bootstrapped [Dessouky JSSC 2001]– Inverter based DAC Drivers
SAR
DAC Driver
DAC Driver
Cap DAC
Cap DAC
VIN
DOUTTime Comp
Delay
16
TSAR Voltage Comparator
• Voltage Comparator– NMOS input devices, PMOS latch only– Uses high VTH devices to read output– Outputs directly feed time comparator 17
CPVINP VINN
CLK CLK
CLK
CLK
CNLatchLatch
TCN TCP
TSAR Time Comparison
• Time references set with internal clocking unit– Current starved
inverter based18
RST
VGP
VGN
Current Starved
Time Latch
Time Latch
To SAR Logic
To SAR Logic
CLK
Internal Clock
Voltage Comparator Regerating
Time Latch Transparent
Voltage Comparator
Resetting
Time Data Latched
Comparator Operations
TSAR Logic Modifications
• Skipping logic blocks determine the next enabled state based on time information 19
DFFD Q
Q
Skipping Logic 1
D Q
DLCH
D Q
DLCH
TP
TN
DFFD Q
Q
Skipping Logic 2
D Q
DLCH
D Q
DLCH
TP
TN
DFFD Q
Q
D Q
DLCH
D Q
DLCH
TP
TN
SLN
SL3
DFF3
UP1 UP2 UPN
DN1 DN2 DNN
CK
DFFS Q
R Q
RST
Time Comp P
Time Comp N
CP
CN
TP
TN
CK
TSAR State Machine Enhancements
• TSPC DFF optimized for SAR ring counter– Reduces energy on “00” state with simple asy. reset– Saves 70% of state machine power – Increases setup time by 50%
bN-1 bN ETSPC EPROP
7.93fJ 0.10fJ
3.67fJ
6.69fJ0.02fJ
3.73fJ
9.10fJ0.02fJ
0
0
11
0
1
01
20
CK
CK
CK
CK
RSTD
Q
TSAR Reference 3 Calibration
• Reference Calibration Sets Third Reference– No static power, reference stored as capacitor voltage– First 2 references are coarse and only used for
redundancy in groups 1 and 2– Works on the principle that latter stage distribution
become more white [Levy TCASI 2011]
Mod-N ACC
Dynamic CP
01 (+1)
10,00 (-1)
Roll Up
Roll DN
VTREF3
For ¼ Time Level, 50% of codes should equal “01”
21
TSAR Die Photo
• Layout Specs– JAZZ 0.13µm
CMOS– Active Area =
0.056mm²
311µm
180µm
Analog CoreSAR and
Logic
Cap Drivers
Capacitor
Array
Capacitor
Array
Calibration
Circuit
200µm x
80µm
Cap Drivers
22
TSAR Outline
• SAR Motivation
• TSAR Structure and Benefits
• Implementation
• Measured Results– Resolution– Power Distribution
• Conclusions23
TSAR Measured Results
TSAR Frequency Response Nyquist ENOB vs. CLK Frequency
8 MHz CLKVDD = 0.8VFOM = 16.9fJ/C-S
24
TSAR Measured Results
TSAR Frequency Response Nyquist ENOB vs. CLK Frequency
8 MHz CLKVDD = 0.8VFOM = 16.9fJ/C-S
25
TSAR Power ConsumptionMeasured TSAR Power vs. Input TSAR Power Breakdown
40%
38%
6%
4%8%
4%
Comparator Cap Array/DriversTime Comparison Bootstrap SwitchSAR Logic Ref/CLK Gen
26
TSAR Performance Summary
CLK Freq. (MHz) 8 8 20 20
Supply (V) 0.8 1.2 0.8 1.2
Input Freq. (MHz) 4 4 10 10
Total Power (µW) 84 231 202 526
SNDR (dB) 57.6 59.6 53.3 55.7
SFDR (dB) 76.1 76.8 74.1 78.6
FOM (fJ/CS) 16.8 36.8 26.8 52.8
27
TSAR Outline
• SAR Motivation
• TSAR Structure and Benefits
• Implementation
• Measured Results
• Conclusions
28
TSAR Summary
• Accuracy Improvements– Redundancy, Residue Shaping, and Calibration
• Speed Improvements– Reduced comp. delay and capacitor settling time
• Power Reduction– Stage Skipping, DAC activity reduction, residue
shaping, and logic modifications
• Implementation– Working chip demonstrated in 0.13um CMOS
29
Questions
30
Backup Slides
31
References I
1. V. Hariprasath, J. Guerber, S.-H. Lee, and U. Moon, “Merged capacitor switching based SAR ADC with highest switching energy-efficiency,” Electron. Lett., vol. 46, pp. 620-621, Apr. 29, 2010.
2. Y. Zhu, C.-H. Chan, et al., “A 10b 100MS/s reference-free SAR ADC in 90nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, pp. 1111-1121, Jun. 2010.
3. J. Yang, T. Naing, and R. Brodersen, “A 1 GS/s 6b 6.7mW successive approximation ADC using asynchronous processing,” IEEE J. Solid-State Circuits, vol. 45, no. 8, pp. 1469-1478, Aug. 2010.
4. C.-C. Liu, S.-J. Chang, et al., “A 1V 11fJ/conversion-step 10b 10MS/s asynchronous SAR ADC in 0.18um CMOS,” IEEE Symp. On VLSI Circuits, June 2010, pp. 241-242.
32
References II
5. B. Levy, “A propagation analysis of residual distribution in pipeline ADCs,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 58, no. 10, pp. 2366-2376, Oct. 2011.
6. M. Dessouky, A. Kaiser, “Very low-voltage digital-audio ΔΣ modulator with 88-dB dynamic range using local switch bootstrapping,” IEEE J. Solid-State Circuits, vol. 36, no. 3, Mar. 2001.
33
TSAR Time Comparator
• Internal Clocking Circuit Details– 2 phases, comparator asynchronously reset
34
SAR Registers,
Phase selector
and Reference selector
RSTVGP
VGN
CKSET
CKRST
CKSET
CKRST
CKRST
CKSET
Current Starved
TSAR Time Comparator
• Time Comparator– Gated Inverter
Based– Device strength
based on speed and accuracy
– Outputs fed to SAR Registers
35
CLK
CP
TNP
Internal Clock
Voltage Comparator Regerating
Time Comparator Transparent
Voltage Comparator
Resetting
Time Data Latched
Comparator Operations
TSAR Time Comparison
• CLK pulse width sets time comparison threshold36
Internal Clock
Voltage Comparator Regerating
Time Latch Transparent
Voltage Comparator
Resetting
Time Data Latched
Comparator Operations