Post on 21-Aug-2020
A 0.84ps-LSB 2.47mW Time-to-Digital
Converter Using Charge Pump and
SAR-ADC
Zule Xu, Seungjong Lee, Masaya
Miyahara, and Akira Matsuzawa
Tokyo Institute of Technology, Japan
2Outline
• Motivation
• Issues of conventional techniques
• Proposed TDC
• Measured performance
• Conclusion
3Motivation
• A fine resolution TDC contributes low in-band phase
noise to a digital PLL
• Example: fv = 4GHz, fref = 40MHz, PN = -120dBc/Hz
tres = 0.87ps !
• Delay-chain’s resolution is limited to its unit delay
fv
fref
...td td td
Dout
...
Encoder
Counter
TDC
DLF DCO
Σ
FCW fv
fref
4Motivation
• For finer resolution, more energy, more area, or
more conversion times are traded off
• Is there a solution for the best balance?
0
100
200
300
400
0 0.02 0.04 0.06 0.08 0.1
Fo
M [
fJ/b
it]
Area [mm2]
5.5ps
1.25ps [JSSC`12]3.75ps
4.7ps
4.8ps Noise shaping1ps [JSSC`09]
5Issues of Recent Techniques
• Vernier chain
– PVT and jitter effects
– Arbiter’s metastability
(unacceptable when
the input <= 1ps)
CK1
CK2
...td1 td1
...
...td2 td2
...D[0]
Delay
chain
CK1
CK2
Encoder
...
Dout
TADelay
chain
• Pipeline
– Nonlinearity of the time
amplifier (TA)
– Mismatch
6Issues of Recent Techniques
• Stochastic
– Short linear range
– Highly dependent on
layout and process
N arbiters w/ mismatches
CK1
CK2
Dout
• Noise shaping
– Low input signal
bandwidth
– Requires a fast clock
for the counter
Σ
(Counter)
Digital-to-time
converter
QTin
Dout
CKfast
7Issues of a Previous Technique
• Time-to-amplitude conversion has achieved
fine resolution but…
• Fast clock necessary
• Large capacitance
• Susceptible to
leakage
• Low speed
Dout
Counter
CKfastRST V1
Tin
I
RST
I/N
EN
Fa
lling
ed
ge
trigg
ere
d
C
M*C
V2
V1
V2
...
Tin
EN
CKfast
tres = Tckfast/(M*N)
[E.R.Ruotsalainen, et.al,
pp.1507-1510, JSSC 2000]
tres = 32ps, 0.5um BiCMOS
8Time-to-Charge Conversion
• Time-to-charge conversion suggests the
potential for extremely fine resolution
ADCDout
Tin
Vout
CI RST
C 1pF
I 1mA
Vlsb 1mV
tres 1ps
tres = C*Vlsb/I
• Thermal noise restricts C and I
9Thermal Noise
• Noise increases with integration time (Δt)
• Trade-off exists between power (I) and area (C)
d
m
res
lsbvn
I
g
t
V
C
tkT
4
2
A constant for transistor sizing
Crdsin2
σvn2
ΔtΔt
256 512 768 1024
0.1
0.2
0.3
0.4
0.5
t [ps]
vn [
LS
B]
tres
= 1ps, 10-bit, Vlsb
= 1mV, gm
/Id = 9
0.5pF, 0.5mA
1pF, 1mA
2pF, 2mA
10Proposal
• Time-to-charge conversion on a SAR-ADC
• Short Ton is required to suppress the noise; Ton ≈
200ps in this design
SAR-ADC
Dout
...
...
Cu 2n*Cu
...
...
Cu 2n*Cu
Charge pump
...
CKadc
Vp
Vn
Ton
UP
CK2
CK1R
RDN
QD
QD
PFD
11Noise and Speed
1) Thermal noise from the charge pump accumulated
during (Tin+Ton)
2) SAR-ADC should be faster than 40MS/s
Tin
Ton
CK1,CK2
UP, DN
Vp, Vn
Tin
ΔV
CKadc
Sampling Conversion Sampling
...
... ...
...
Dout
< 24ns
Dn Dn+1
~25ns
12SAR-ADC
• 12-bit topology
– 10-bit ENOB@40MS/s
– 1.6mW@1.0V power supply
[S. Lee, SSDM 2013, to be presented]
• Dynamic comparator
– Low power
• Metal-Oxide-Metal capacitor
– High density
• Same pitch of cap. and switch
– Better matching and
scalabilityUnit capacitor
and switch
Top
Bottom
MOS
SW
Top
Bottom
MOS
SW
...
13Scaling of the SAR-ADC
• Down scaling lower power and smaller area
shorter range but not harmful for an integer-N PLL
• Resolution and intrinsic SNR are not degraded since
the required charges are not changed
oninpmnm
cpreslsb
diffvn
lsb
TTgg
ItCV
kT
V
1
2
12
,
2
Other
LSBs8Cu 32Cu 64Cu16Cu
Other
LSBs8Cu 16Cu
Other
LSBs
12-bit
10-bit 8-bit Unchanged Q2
Intrinsic SNR:
14Charge Pump
• The CMFB matches the currents of PMOS and
NMOS
Vbp_fb
Vcp
RSTUP UP
DN
RST
UP
DNDN
DN
Vcn
Vbn VbpVcm
Φ2
Φ1
Vp Vn
UPVm
Φ1 Φ2
Settled
voltage
• Conventional
– Amplifier-based
CMFB
• Proposal
– Switched-capacitor
CMFB
– For low power and
low voltage
Reset mode
15Charge Pump
• Other mismatches contribute to a static offset
• It can be canceled in the digital domain
Vbp_fb
Vcp
RSTUP UP
DN
RST
UP
DNDN
DN
Vcn
Vbn VbpVcm
Φ2
Φ1
Vp Vn
UPVm
Φ1 Φ2
Held voltage
Charging mode
-4 -3 -2 -1 0 1 2 3 40
10
20
30
40
50
(Vp-Vn) [mV]
Co
un
t
σ ≈ 1mV
Monte-Calo simulation
of the output voltage
(Δt=0, 1pF load cap.)
16Implementation
• CMOS 65nm, core area = 0.06mm2
• Measurement setups
SG1
SG2
TDCLogic
analyzer
40MHz
40MHz + 5Hz
Pulse
generator
Splitter TDCLogic
analyzerΔt
~100ps rising time
17Measurement
• DNL and performance summary
0 32 64 96 128 160 192 224 256
-1
0
1
DNL and INL in 8-bit with 0.84ps/LSB
DN
L [
LS
B]
0 32 64 96 128 160 192 224 256
-2
0
2
Code
INL
[L
SB
]
Performance Value
CMOS [nm] 65
Supply [V] 1.0
Conv. Rate [MS/s] 40
Power [mW] 2.47
Resolution [ps] 0.84
Range [bits] 8
DNL [LSB] -0.7/1.0
INL [LSB] -2.7/1.7
18
113 114 115 116 1170
0.5
1
1.5
2
2.5x 10
5
Code
Co
un
ts
67 68 69 70 71 72 73 74 75 76 770
0.5
1
1.5
2
2.5x 10
5
Code
Co
un
ts
Measurement
• Single-shot precision: < 1LSB
• The thermal noise increases with longer input
time interval
Δt=11ps
σ=0.24LSBΔt=47ps
σ=0.45LSB
19Performance Comparison
• Best balance is achieved
JSSC’10 VLSI’11 VLSI’12 ESSIRC’10 This workImproved
(Simulated)
Type Vernier Pipeline Noise Shaping Stochastic Charge Charge
CMOS [nm] 65 130 130 65 65 65
Supply [V] 1.2 1.3 1.2 1.2 1.0 1.2
Resolution [ps] 4.8 0.63 3 3 0.84 1
Range [bits] 7 11 11 4 8 10
DNL [LSB] <1 0.5 N/A 1.4 -0.7/1.0 -0.2/0.2
INL [LSB] 3.3 2 N/A 1.5 -2.7/1.7 -2.7
Frequency
[MHz]50 65
90
(OSR:16)40 40 100
Power [mW] 1.7 10.5 3.2 8 2.47 4
Area [mm2] 0.02 0.32 0.43 0.04 0.06 0.018
20Energy and Area Efficiencies
• Best balance is achieved
NFrequencyPowerFoM 2//
Energy efficiency:NBWPowerFoM 2//2/or
0
100
200
300
400
0 0.02 0.04 0.06 0.08 0.1
Fo
M [
fJ/b
it]
Area [mm2]
5.5ps
1.25ps [JSSC`12]3.75ps
4.7ps
4.8ps Noise shaping1ps [JSSC`09]
0.84ps [This work]
1ps[Improved, simulated]
21Conclusion
• The proposed TDC has achieved 0.84ps resolution,
2.47mW power consumption, and 0.06mm2 area
• The proposed TDC suggests the best balance
among resolution, energy, area, and conversion
times
• The proposed TDC has no issues from delay chains,
TAs, or arbiters
• The proposed TDC can be a practical solution for
digital PLLs
22Acknowledgement
• This work was partially supported by
HUAWEI, Berkeley Design Automation for the
use of the Analog Fast SPICE(AFS) Platform,
and VDEC in collaboration with Cadence
Design Systems, Inc.
23
Thank you
for your interest!
Zule Xu,
xuzule@ssc.pe.titech.ac.jp