Post on 30-Oct-2021
8-Bit, 40/80/100 MSPSDual A/D Converter
AD9288
Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
FEATURES Dual 8-bit, 40 MSPS, 80 MSPS, and 100 MSPS ADC Low power: 90 mW at 100 MSPS per channel On-chip reference and track-and-hold 475 MHz analog bandwidth each channel SNR = 47 dB @ 41 MHz 1 V p-p analog input range each channel Single 3.0 V supply operation (2.7 V to 3.6 V) Standby mode for single-channel operation Twos complement or offset binary output mode Output data alignment mode Pin-compatible 10-bit upgrade available
APPLICATIONS Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes I and Q communications
FUNCTIONAL BLOCK DIAGRAM
0058
5-00
1
AD9288
T/H
REF
T/H ADC
OU
TPU
T R
EGIS
TER
8 8
8 8
OU
TPU
T R
EGIS
TER
TIMING
TIMING
VDD
SELECT 1
SELECT 2
DATA FORMATSELECT
D7B–D0B
D7A–D0A
VDDGNDVD
ENCA
ENCB
AINAAINA
AINBAINB
REFINAREFOUT
REFINB
ADC
Figure 1.
GENERAL DESCRIPTION The AD9288 is a dual 8-bit monolithic sampling analog-to-digital converter with on-chip track-and-hold circuits. It is optimized for low cost, low power, small size, and ease of use. The product operates at a 100 MSPS conversion rate with outstanding dynamic performance over its full operating range. Each channel can be operated independently.
The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power supply and an Encode clock for full-performance operation. No external reference or driver components are required for many applications. The digital outputs are TTL/CMOS-compatible, and a separate output power supply pin supports interfacing with 3.3 V or 2.5 V logic.
The Encode input is TTL/CMOS-compatible, and the 8-bit digital outputs can be operated from 3.0 V (2.5 V to 3.6 V) supplies. User-selectable options offer a combination of standby modes, digital data formats, and digital data timing schemes. In standby mode, the digital outputs are driven to a high impedance state.
Fabricated on an advanced CMOS process, the AD9288 is available in a 48-lead surface-mount plastic package (7 mm × 7 mm, 1.4 mm LQFP) specified over the industrial temperature range (–40°C to +85°C). The AD9288 is pin-compatible with the 10-bit AD9218, facilitating future system migrations.
AD9288* PRODUCT PAGE QUICK LINKSLast Content Update: 02/23/2017
COMPARABLE PARTSView a parametric search of comparable parts.
DOCUMENTATIONApplication Notes
• AN-302: Exploit Digital Advantages in an SSB Receiver
• AN-835: Understanding High Speed ADC Testing and Evaluation
Data Sheet
• AD9288: 8-Bit, 40/80/100 MSPS Dual A/D Converter Data Sheet
TOOLS AND SIMULATIONS• AD9288 IBIS Models
REFERENCE MATERIALSTechnical Articles
• Correlating High-Speed ADC Performance to Multicarrier 3G Requirements
• DNL and Some of its Effects on Converter Performance
• Single Chip Realizes Direct-Conversion Rx
DESIGN RESOURCES• AD9288 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
DISCUSSIONSView all AD9288 EngineerZone Discussions.
SAMPLE AND BUYVisit the product page to see pricing options.
TECHNICAL SUPPORTSubmit a technical question or find your regional support number.
DOCUMENT FEEDBACKSubmit feedback for this data sheet.
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
AD9288
Rev. C | Page 2 of 24
TABLE OF CONTENTS Specifications..................................................................................... 3
Explanation of Test Levels ........................................................... 4 Timing Diagrams.......................................................................... 5
Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ............................................. 9 Test Circuits..................................................................................... 12 Terminology .................................................................................... 13 Theory of Operation ...................................................................... 14
Using the AD9288 ...................................................................... 14 Encode Input............................................................................... 14 Digital Outputs ........................................................................... 14 Analog Input ............................................................................... 14 Voltage Reference ....................................................................... 14
Timing ......................................................................................... 14 User-Selectable Options ............................................................ 14
AD9218/AD9288 Customer PCB BOM...................................... 15 Evaluation Board ............................................................................ 16
Power Connector........................................................................ 16 Analog Inputs ............................................................................. 16 Voltage Reference ....................................................................... 16 Clocking....................................................................................... 16 Data Outputs............................................................................... 16 Data Format/Gain ...................................................................... 16 Timing ......................................................................................... 16 Troubleshooting.......................................................................... 20
Outline Dimensions ....................................................................... 21 Ordering Guide .......................................................................... 21
REVISION HISTORY
12/04—Rev. B to Rev. C
Change to Absolute Maximum Ratings......................................... 7 Replaced Evaluation Board Section ............................................. 16 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 21
2/02—Rev. A to Rev. B
Edits to ABSOLUTE MAXIMUM RATINGS .............................. 3
1/01—Rev. 0 to Rev. A
2/99—Revision 0: Initial Version
AD9288
Rev. C | Page 3 of 24
SPECIFICATIONS VDD = 3.0 V; VD = 3.0 V, differential input; external reference, unless otherwise noted.
Table 1. Test AD9288BST-100 AD9288BST-80 AD9288BST-40 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION 8 8 8 Bits
DC ACCURACY Differential Nonlinearity 25°C I ± 0.5 +1.25 ± 0.5 +1.25 ± 0.5 +1.25 LSB Full VI 1.50 1.50 1.50 LSB Integral Nonlinearity 25°C I ± 0.50 +1.25 ± 0.50 +1.25 ± 0.50 +1.25 LSB Full VI 1.50 1.50 1.50 LSB No Missing Codes Full VI Guaranteed Guaranteed Guaranteed Gain Error1 25°C I –6 ± 2.5 +6 –6 ± 2.5 +6 –6 ± 2.5 +6 % FS Full VI –8 +8 –8 +8 –8 +8 % FS Gain Tempco1 Full VI 80 80 80 ppm/°C Gain Matching 25°C V ±1.5 ±1.5 ±1.5 % FS Voltage Matching 25°C V ±15 ±15 ±15 mV
ANALOG INPUT Input Voltage Range (with
Respect to AIN) Full V ±512 ±512 ±512 mV p-p
Common-Mode Voltage Full V 0.3 × VD
0.3 × VD 0.3 × VD
0.3 × VD
0.3 × VD 0.3 × VD
0.3 × VD
0.3 × VD 0.3 × VD
V
–0.2 +0.2 –0.2 +0.2 –0.2 +0.2 Input Offset Voltage 25°C I –35 ±10 +35 –35 ± 10 +35 –35 ± 10 +35 mV Full VI –40 +40 –40 +40 –40 +40 mV Reference Voltage Full VI 1.2 1.25 1.3 1.2 1.25 1.3 1.2 1.25 1.3 V Reference Tempco Full VI ± 130 ± 130 ± 130 ppm/°C Input Resistance 25°C I 7 10 13 7 10 13 7 10 13 kΩ Full VI 5 16 5 16 5 16 Input Capacitance 25°C V 2 2 2 pF Analog Bandwidth, Full
Power 25°C V 475 475 475 MHz
SWITCHING PERFORMANCE Maximum Conversion Rate Full VI 100 80 40 MSPS Minimum Conversion Rate 25°C IV 1 1 1 MSPS Encode Pulse Width High (tEH) 25°C IV 4.3 1000 5.0 1000 8.0 1000 ns Encode Pulse Width Low (tEL) 25°C IV 4.3 1000 5.0 1000 8.0 1000 ns Aperture Delay (tA) 25°C V 300 300 300 ps Aperture Uncertainty (Jitter) 25°C V 5 5 5 ps rms Output Valid Time (tV)2 Full VI 2 3.0 2 3.0 2 3.0 ns Output Propagation Delay (tPD)2
Full VI 4.5 6.0 4.5 6.0 4.5 6.0 ns
DIGITAL INPUTS Logic 1 Voltage Full VI 2.0 2.0 2.0 V Logic 0 Voltage Full VI 0.8 0.8 0.8 V Logic 1 Current Full VI ± 1 ± 1 ± 1 µA Logic 0 Current Full VI ± 1 ± 1 ± 1 µA Input Capacitance 25°C V 2.0 2.0 2.0 pF
DIGITAL OUTPUTS3 Logic 1 Voltage Full VI 2.45 2.45 2.45 V Logic 0 Voltage Full VI 0.05 0.05 0.05 V
POWER SUPPLY Power Dissipation4 Full VI 180 218 171 207 156 189 mW Standby Dissipation4, 5 Full VI 6 11 6 11 6 11 mW Power Supply Rejection
Ratio (PSRR) 25°C I 8 20 8 20 8 20 mV/V
AD9288
Rev. C | Page 4 of 24
Test AD9288BST-100 AD9288BST-80 AD9288BST-40 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit
DYNAMIC PERFORMANCE6 Transient Response 25°C V 2 2 2 ns Overvoltage Recovery Time 25°C V 2 2 2 ns Signal-to-Noise Ratio (SNR)
(without Harmonics)
fIN = 10.3 MHz 25°C I 47.5 47.5 44 47.5 dB fIN = 26 MHz 25°C I 47.5 44 47 dB fIN = 41 MHz 25°C I 44 47.0 dB
Signal-to-Noise Ratio (SINAD) (with Harmonics)
fIN = 10.3 MHz 25°C I 47 47 44 47 dB fIN = 26 MHz 25°C I 47 44 47 dB fIN = 41 MHz 25°C I 44 47 47 dB
Effective Number of Bits fIN = 10.3 MHz 25°C I 7.5 7.5 7.0 7.5 Bits fIN = 26 MHz 25°C I 7.5 7.0 7.5 Bits fIN = 41 MHz 25°C I 7.0 7.5 7.5 Bits
Second Harmonic Distortion fIN = 10.3 MHz 25°C I 70 70 55 70 dBc fIN = 26 MHz 25°C I 70 55 70 dBc fIN = 41 MHz 25°C I 55 70 70 dBc
Third Harmonic Distortion fIN = 10.3 MHz 25°C I 60 60 55 60 dBc fIN = 26 MHz 25°C I 60 55 60 dBc fIN = 41 MHz 25°C I 52 60 60 dBc
Two-Tone Intermod Distortion (IMD)
fIN = 10.3 MHz 25°C V 60 60 60 dBc
1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.25 V external reference). 2 tV and tPD are measured from the 1.5 V level of the Encode input to the 10%/90% levels of the digital outputs swing. The digital output load during test is not to exceed
an ac load of 10 pF or a dc current of ±40 µA. 3 Digital supply current based on VDD = 3.0 V output drive with < 10 pF loading under dynamic test conditions. 4 Power dissipation measured under the following conditions: fS = 100 MSPS, analog input is –0.7 dBFS, both channels in operation. 5 Standby dissipation calculated with Encode clock in operation. 6 SNR/harmonics based on an analog input voltage of –0.7 dBFS referenced to a 1.024 V full-scale input range.
EXPLANATION OF TEST LEVELS Level Description I 100% production tested. II 100% production tested at 25°C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range;
100% production tested at temperature extremes for military devices.
AD9288
Rev. C | Page 5 of 24
TIMING DIAGRAMS
0058
5-00
3
SAMPLE N SAMPLE N + 1
SAMPLE N + 2 SAMPLE N + 3 SAMPLE N + 4
SAMPLE N + 5
DATA N – 4
DATA N – 4
DATA N – 3 DATA N – 2 DATA N – 1 DATA N DATA N + 1
AINA, AINB
ENCODE A, B
D7A–D0A
D7B–D0B DATA N – 3 DATA N – 2 DATA N – 1 DATA N DATA N + 1
tEH1/fs
tEL
tA
tPD tV
Figure 2. Normal Operation, Same Clock (S1 = 1, S2 = 0) Channel Timing
0058
5-00
4
SAMPLEN
SAMPLEN + 1
SAMPLEN + 2
SAMPLEN + 3
SAMPLEN + 4
AINA, AINB
ENCODE A
ENCODE B
D7A–D0A
D7B–D0B
tEH 1/fstEL
tA
tPDtV
DATA N – 7 DATA N – 5 DATA N – 3 DATA N – 1 DATA N + 1 DATA N + 3
DATA N – 8 DATA N – 6 DATA N – 4 DATA N – 2 DATA N DATA N + 2
Figure 3. Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing
AD9288
Rev. C | Page 6 of 24
0058
5-00
5
SAMPLEN
SAMPLEN + 1
SAMPLEN + 2
SAMPLEN + 3
SAMPLEN + 4
AINA, AINB
ENCODE A
ENCODE B
D7A–D0A
D7B–D0B
DATA N – 8 DATA N – 6 DATA N – 4 DATA N – 2 DATA N DATA N + 2
DATA N – 9 DATA N – 7 DATA N – 5 DATA N – 3 DATA N – 1 DATA N + 1
tEH 1/fstEL
tA
tPDtV
Figure 4. Data Align with Two Clock Sources (S1 = 1, S2 = 1) Channel Timing
AD9288
Rev. C | Page 7 of 24
ABSOLUTE MAXIMUM RATINGS
Table 2. Parameter Rating VD, VDD 4 V Analog Inputs –0.5 V to VD + 0.5 V Digital Inputs –0.5 V to VDD + 0.5 V VREF IN –0.5 V to VD + 0.5 V Digital Output Current 20 mA Operating Temperature –55°C to +125°C Storage Temperature –65°C to +150°C Maximum Junction Temperature 150°C Maximum Case Temperature 150°C Thermal Impedance θja 57°C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
AD9288
Rev. C | Page 8 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
0058
5-00
2
GNDAINA
V DEN
CB
V DD
GN
D(M
SB) D
7 BD
6 BD
5 BD
4 BD
3 BD
2 BD
1 BD
0 B
AINADFS
REFINAREFOUTREFINB
S1S2
AINBAINBGND
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 39 38 3743 42 41 40
PIN 1IDENTIFIER
NCNC
VDD
GND
GNDVDVD
NC = NO CONNECT
GND
GNDVDD
NCNC
AD9288TOP VIEW
(Not to Scale)
V D ENC
AV D
DG
ND
D7 A
(MSB
)D
6 AD
5 AD
4 AD
3 AD
2 AD
1 AD
0 A
Figure 5. Pin Configuration
Table 3. Pin No. Name Description 1, 12, 16, 27, 29, 32, 34, 45
GND Ground
2 AINA Analog Input for Channel A. 3 AINA Analog Input for Channel A (Complementary).
4 DFS Data Format Select. Offset binary output available if set low. Twos complement output available if set high. 5 REFINA Reference Voltage Input for Channel A. 6 REFOUT Internal Reference Voltage. 7 REFINB Reference Voltage Input for Channel B. 8 S1 User Select 1. Refer to Table 4. Tied with respect to VD. 9 S2 User Select 2. Refer to Table 4. Tied with respect to VD. 10 AINB Analog Input for Channel B (Complementary).
11 AINB Analog Input for Channel B. 13, 30, 31, 48 VD Analog Supply (3 V). 14 ENCB Clock Input for Channel B. 15, 28, 33, 46 VDD Digital Supply (3 V). 17–24 D7B–D0 B Digital Output for Channel B. 25, 26, 35, 36 NC Do Not Connect. 37–44 D0A–D7 A Digital Output for Channel A. 47 ENC A Clock Input for Channel A.
AD9288
Rev. C | Page 9 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
0
–10
–20
–30
–40
–50
–60
–70
–80
–90 0058
5-00
6SAMPLE
dB
ENCODE = 100MSPSAIN = 10.3MHzSNR = 48.52dBSINAD = 48.08dBSECOND HARMONIC = –62.54dBcTHIRD HARMONIC = –63.56dBc
Figure 6. Spectrum: fS = 100 MSPS, fIN = 10 MHz, Single-Ended Input
0
–10
–20
–30
–40
–50
–60
–70
–80
–90 0058
5-00
7
SAMPLE
dB
ENCODE = 100MSPSAIN = 41MHzSNR = 47.87dBSINAD = 46.27dBSECOND HARMONIC = –54.10dBcTHIRD HARMONIC = –55.46dBc
Figure 7. Spectrum: fS = 100 MSPS, fIN = 41 MHz, Single-Ended Input
0
–10
–20
–30
–40
–50
–60
–70
–80
–90 0058
5-00
8
SAMPLE
dB
ENCODE = 100MSPSAIN = 76MHzSNR = 47.1dBSINAD = 43.2dBSECONDHARMONIC = –52.2dBcTHIRD HARMONIC = –51.5dBc
Figure 8. Spectrum: fS = 100 MSPS, fIN = 76 MHz, Single-Ended Input
72
68
400 10 20 30 40 50 60 70 80 90
44
48
52
56
60
64
0058
5-00
9
MHz
dB
2ND
3RD
ENCODE RATE = 100MSPS
Figure 9. Harmonic Distortion vs. AIN Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–90 0058
5-01
0
SAMPLE
dB
ENCODE = 100MSPSAIN1 = 9.3MHzAIN2 = 10.3MHzIMD = –60.0dBc
Figure 10. Two-Tone Intermodulation Distortion
50
48
46
44
42
40
38
360 10 20 30 40 50 60 70 80 90
0058
5-01
1
MHz
dB
ENCODE RATE = 100MSPS
SNR
SINAD
Figure 11. SINAD/SNR vs. AIN Frequency
AD9288
Rev. C | Page 10 of 24
49
48
47
46
4530 40 50 60 70 80 90 100 110
0058
5-01
2
MSPS
dB
SINAD
SNRAIN = 10.3MHz
Figure 12. SINAD/SNR vs. Encode Rate
SINAD
SNR50
46
38
42
34
307.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0
0058
5-01
3
ENCODE HIGH PULSE WIDTH (ns)
dB
AIN = 10.3MHz
Figure 13. SINAD/SNR vs. Encode Pulse Width High
0.5
–5.5
–5.0
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0 100 200 300 400 500 600
0058
5-01
4
BANDWIDTH (MHz)
dB
ENCODE RATE = 100MSPS
–3dB
Figure 14. ADC Frequency Response: fS = 100 MSPS
190
185
180
175
170
165
160
155
150
145
1400 100908070605040302010
0058
5-01
5
MSPS
POW
ER (m
W)
AIN = 10.3MHz
Figure 15. Analog Power Dissipation vs. Encode Rate
SNR
SINAD
48.0
47.5
47.0
46.5
46.0
45.5
45.0
44.5
44.0
43.5–40 25 85
0058
5-01
6
TEMPERATURE (°C)
dB
ENCODE RATE = 100MSPSAIN = 10.3MHz
Figure 16. SINAD/SNR vs. Temperature
0.6
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
–40 25 85
0058
5-01
7
TEMPERATURE (°C)
% G
AIN
ENCODE RATE = 100MSPSAIN = 10.3MHz
Figure 17. ADC Gain vs. Temperature (with External 1.25 V Reference)
AD9288
Rev. C | Page 11 of 24
2.0
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
0058
5-01
8
CODE
LSB
Figure 18. Integral Nonlinearity
1.00
–1.00
–0.75
–0.50
–0.25
0
0.25
0.50
0.75
0058
5-01
9
CODE
LSB
Figure 19. Differential Nonlinearity
1.3
1.2
1.1
1.0
0.9
0.8
0.70 0.25 0.50 0.75 1.00 1.25 1.50 1.75
0058
5-02
0
LOAD (mA)
V REF
OU
T (V
)
ENCODE = 100MSPSVD = 3.0VTA = 25°C
Figure 20. Voltage Reference Out vs. Current Load
AD9288
Rev. C | Page 12 of 24
TEST CIRCUITS
0058
5-02
1
AINAIN
28kΩ
12kΩ
28kΩ
12kΩ
VD
Figure 21. Equivalent Analog Input Circuit
0058
5-02
2VD
VBIAS
REFIN
Figure 22. Equivalent Reference Input Circuit
0058
5-02
3
ENCODE
VD
Figure 23. Equivalent Encode Input Circuit
0058
5-02
4
VDD
OUT
Figure 24. Equivalent Digital Output Circuit
0058
5-02
5
VD
OUT
Figure 25. Equivalent Reference Output Circuit
AD9288
Rev. C | Page 13 of 24
TERMINOLOGY Analog Bandwidth (Small Signal) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.
Aperture Delay The delay between a 50% crossing of Encode and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay.
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
Encode Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that the Encode pulse should be left in Logic 1 state to achieve rated performance; pulse width low is the minimum time Encode pulse should be left in low state. At a given clock rate, these specs define an acceptable Encode duty cycle.
Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” determined by a least square curve fit.
Minimum Conversion Rate The Encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate The Encode rate at which parametric testing is performed.
Output Propagation Delay The delay between a 50% crossing of Encode and the time when all output data bits are within valid logic levels.
Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage.
Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral compo-nents, including harmonics but excluding dc.
Signal-to-Noise Ratio (SNR) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious compo-nent may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered), or in dBFS (always related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal level is lowered), or in dBFS (always related back to converter full scale).
Worst Harmonic The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc.
AD9288
Rev. C | Page 14 of 24
THEORY OF OPERATION The AD9288 ADC architecture is a bit-per-stage pipeline-type converter utilizing switch capacitor techniques. These stages determine the 5 MSBs and drive a 3-bit flash. Each stage provides sufficient overlap and error correction, allowing optimization of comparator accuracy. The input buffers are differential, and both sets of inputs are internally biased. This allows the most flexible use of ac or dc and differential or single-ended input modes. The output staging block aligns the data, carries out the error correction, and feeds the data to output buffers. The set of output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. There is no discernible difference in performance between the two channels.
USING THE AD9288 Good high speed design practices must be followed when using the AD9288. To obtain maximum benefit, decoupling capacitors should be physically as close as possible to the chip, minimizing trace and via inductance between chip pins and capacitor (0603 surface-mount capacitors are used on the AD9288/PCB evaluation board). It is recommended to place a 0.1 µF capacitor at each power-ground pin pair for high frequency decoupling, and to include one 10 µF capacitor for local low frequency decoupling. The VREF IN pin should also be decoupled by a 0.1 µF capacitor. It is also recommended to use a split power plane and a contiguous ground plane (see the Evaluation Board section). Data output traces should be short (< 1 inch), minimizing on-chip noise at switching.
ENCODE INPUT Any high speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. A track-and-hold circuit is essentially a mixer. Any noise, distortion, or timing jitter on the clock is combined with the desired signal at the A/D output. For that reason, considerable care has been taken in the design of the Encode (Clock) input of the AD9288, and the user is advised to give commensurate thought to the clock source. The Encode input is fully TTL/CMOS-compatible.
DIGITAL OUTPUTS The digital outputs are TTL/CMOS-compatible for lower power consumption. During standby, the output buffers transition to a high impedance state. A data format selection option supports either twos complement (set high) or offset binary output (set low) formats.
ANALOG INPUT The analog input to the AD9288 is a differential buffer. For best dynamic performance, impedance at AIN and AIN should match. Special care was taken in the design of the analog input stage of the AD9288 to prevent damage and corruption of data when
the input is overdriven. The nominal input range is 1.024 V p-p centered at VD × 0.3.
VOLTAGE REFERENCE A stable and accurate 1.25 V voltage reference is built into the AD9288 (REFOUT). In normal operation, the internal reference is used by strapping Pins 5 (REFINA) and 7 (REFINB) to Pin 6 (REFOUT). The input range can be adjusted by varying the reference voltage applied to the AD9288. No appreciable degradation in performance occurs when the reference is adjusted ±5%. The full-scale range of the ADC tracks reference voltage, which changes linearly.
TIMING The AD9288 provides latched data outputs, with four pipeline delays. Data outputs are available one propagation delay (tPD) after the rising edge of the Encode command (see Figure 2, Figure 3, and Figure 4). The length of the output data lines and loads placed on them must be minimized to reduce transients within the AD9288. These transients can detract from the converter’s dynamic performance.
The minimum guaranteed conversion rate of the AD9288 is 1 MSPS. At clock rates below 1 MSPS, dynamic performance degrades. Typical power-up recovery time after standby mode is 15 clock cycles.
USER-SELECTABLE OPTIONS Two pins are available for a combination of operational modes. These options allow the user to place both channels, excluding the reference, into standby mode, or just the B channel. Both modes place the output buffers and clock inputs into high impedance states.
The other option allows the user to skew the B channel output data by 1/2 of a clock cycle. In other words, if two clocks are fed to the AD9288 and are 180° out of phase, enabling the data align allows Channel B output data to be available at the rising edge of Clock A. If the same Encode clock is provided to both channels and the data align pin is enabled, then output data from Channel B is 180° out of phase with respect to Channel A. If the same Encode clock is provided to both channels and the data align pin is disabled, both outputs are delivered on the same rising edge of the clock.
Table 4. User-Selectable Options S1 S2 Option
0 0 Standby Both Channels A and B.
0 1 Standby Channel B Only. 1 0 Normal Operation (Data Align Disabled). 1 1 Data Align Enabled (data from both channels avail-
able on rising edge of Clock A. Channel B data is delayed a 1/2 clock cycle).
AD9288
Rev. C | Page 15 of 24
AD9218/AD9288 CUSTOMER PCB BOM Table 5. Bill of Materials No. Qty. Reference Designator Device Package Value Comments
1 29 C1, C3-C15, C20, C21, C24, C25, C27, C30–C35, C39–C42
Capacitor 0603 0.1 µF
2 2 C2, C36 Capacitor 0603 15 pF 8138 out 3 7 C16–C19, C26, C37, C38 Capacitor TAJD 10 µF 4 28 E1, E2, E3, E4, E12–E30,
E34–E38 W-HOLE W-HOLE
5 4 H1, H2, H3, H4 MTHOLE MTHOLE 6 5 J1, J2, J3, J4, J5 SMA SMA J2, J3, not placed 7 3 P1, P4, P11 4-pin power connector Post Z5.531.3425.0 Wieland 8 3 P1, P4, P11 4-pin power connector Detachable
Connector 25.602.5453.0 Wieland
9 1 P2, P31 80-pin rt. angle male TSW-140-08- L-D-RA
Samtec
10 4 R1, R2, R32, R34 Resistor 0603 36 Ω R1, R2, R32, R34, not placed
11 9 R3, R7, R11, R14, R22, R23, R24, R30, R51
Resistor 0603 50 Ω R11, R22, R23, R24, R30, R51 not placed
12 17 R4, R5, R8, R9, R10, R12, R13, R20, R33, R35, R36, R37, R40, R42, R43, R50, R53
Resistor 0603 Zero Ω R43, R50 not placed
13 2 R6, R38 Resistor 0603 25 Ω R6, R38 not placed
14 6 R15, R16, R18, R26, R29, R31 Resistor 0603 500 Ω R16, R29 not placed
15 2 R17, R25 Resistor 0603 525 Ω 16 2 R19, R27 Resistor 0603 4 kΩ 17 12 R21, R28, R39, R41, R44,
R46–R49, R52, R54, R55 Resistor 0603 1 kΩ
18 2 T1, T2 Transformer ADT1-1WT Minicircuits 19 1 U1 AD92882 LQFP48 20 2 U2, U3 74LCX821 21 2 U5, U6 SN74VCX86 22 4 U7, U8, U9, U10 Resistor array CTS 47 Ω 768203470G 23 2 U11, U12 AD8138 op amp3
1 P2, P3 are implemented as one physical 80-pin connector SAMTEC TSW-140-08-L-D-RA.2 AD9288/PCB populated with AD9288-100. 3 To use optional amp: place R22, R23, R30, R24, R16, R29, remove R4, R36.
AD9288
Rev. C | Page 16 of 24
EVALUATION BOARDThe AD9218/AD9288 customer evaluation board offers an easy way to test the AD9218 or the AD9288. The compatible pinout of the two parts facilitates the use of one PCB for testing either part. The PCB requires power supplies, a clock source, and a filtered analog source for most ADC testing required.
POWER CONNECTOR Power is supplied to the board via a detachable 12-lead power strip. The minimum 3 V supplies required to run the board are VDD, VDL, and VDD. To allow the use of the optional amplifier path, ±5 V supplies are required.
ANALOG INPUTS Each channel has an independent analog path that uses a wideband transformer to drive the ADC differentially from a single-ended sine source at the input SMAs. The transformer paths can be bypassed to allow the use of a dc-coupled path by using two AD8138 op amps with a simple board modification. The analog input should be band-pass filtered to remove any harmonics in the input signal and to minimize aliasing.
VOLTAGE REFERENCE The AD9288 has an internal 1.25 V voltage reference; an external reference for each channel can be used instead by connecting two external voltage references at the power connector and setting jumpers at E18 and E19. The evaluation board is shipped configured for internal reference mode.
CLOCKING Each channel can be clocked by a common clock input at SMA input ENCODE A/B. The channels can also be clocked independently by a simple board modification. The clock input should be a low jitter sine source for maximum performance.
DATA OUTPUTS The data outputs are latched on-board by two 10-bit latches and drive an 8-pin connector which is compatible with the dual-channel FIFO board available from Analog Devices. This board, together with ADC analyzer software, can greatly simplify ADC testing.
DATA FORMAT/GAIN The DFS/Gain pin can be biased for desired operation at the DFS jumper located at the S1, S2 jumpers.
TIMING Timing on each channel can be controlled if needed on the PCB. Clock signals at the latches or the data ready signals that go to the output 80-pin connector can be inverted if required. Jumpers also allow for biasing of Pins S1 and S2 for power-down and timing alignment control.
AD9288
Rev. C | Page 17 of 24
00585-026
P6P5 P7V D
D
V D V DL
+
++
++
++
C37
10µF
C38
10µF
C16
10µF
C17
10µF
C18
10µF
C19
10µF
C26
10µF
GN
D
–5V
+5V
V DV D
DV D
LV R
EFA
V REF
BV D
L
V DD
GN
DV D
1 2 3 4
P1
V REF
BV R
EFA
GN
DG
ND
1 2 3 4
P4
GN
D–5
V
+5V
GN
D
1 2 3 4
P11
H3
MTH
OLE
6H
1M
THO
LE6
H2
MTH
OLE
6H
4M
THO
LE6
GN
D
VDENCA
VDDGNDD9A(MSB)D8AD7AD6AD5AD4AD3AD2A
C7
0.1µ
F
C8
0.1µ
F
GN
D
GN
D
D1 A
D0 A
GN
DV D
DG
ND
V D
GN
DV D
DG
ND
D0 B
D1 B
C4
0.1µ
F
GN
D
C3
0.1µ
F
GN
D
C1
0.1µ
F
GN
D
D2B
D3B
D4B
D5B
D6B
D7B
D8B
(MSB) D9B
GNDVDD
ENCB
VDC
50.
1µF
C6
0.1µ
F
GN
D
GN
D
GN
D
AM
POU
TA
AM
POU
TB
AM
POU
TAB
REF
OU
T
GN
D
C10
0.1µ
F
C9
0.1µ
F
C11
0.1µ
F
C31
0.1µ
F
C14
0.1µ
F
R4
00Ω
R5
00Ω
R33
00Ω
C15
0.1µ
F
C13
0.1µ
F
R35
00Ω
R1
36Ω R2
36Ω
R36
00Ω
R34
36Ω
R32
36Ω
R6
25Ω
GN
D
GN
D
GN
D
GN
DG
ND
R3
50Ω
GN
D
1 26 5
GN
D
GN
D3
4
34
T2
1 26 5
J4 GN
DA
MPI
NA
AM
PIN
B
AIN
A
J1 GN
DAIN
B
R38
25Ω
R7
50Ω
GN
D
E17
E18E1 E19
E27E3
0E2
E25
VD
VREF
AE2
0
E24
E22
VDE2
9G
ND
E23
E26
VDE2
8
1 2 3 4 5 6 7 8 9 10 11 12
36 35 34 33 32 31 30 29 28 27 26 25
GN
DA
INA
AIN
AD
FS/G
AIN
REF
INA
REF
OU
TR
EFIN
BS1 S2 A
INB
AIN
BG
ND
48
47
46
45
44
43
42
41
40
39
38
37
13
14
15
16
17
18
19
20
21
22
23
24
VDENCA
VDDGNDD9A
D8AD7AD6AD5AD4AD3AD2A
AD
9218
/AD
9288
U1
VDENCBVDDGNDD9B
D8BD7BD6BD5BD4BD3BD2B
D1 A
D0 A
GN
DV D
D
GN
D V D V DG
ND
V DD
GN
DD
0 BD
1 BG
ND
C12
0.1µ
FG
ND
GN
D
GN
D
AM
POU
TBB
R S
ING
LE-E
ND
ED
R S
ING
LE-E
ND
ED
R37
00Ω
C30
0.1µ
F
C39
0.1µ
F
2Y6
3A9
GN
D7
3Y8
1A1
1B2
1Y3
2A4
2B5
VCC 4B 4A 4Y 3B
14 13 12 11 10E4
E3
ENC
XA
ENC
XAEN
CA G
ND
GN
D
GN
D
GN
D
VDL
TIEA
VDL
VDL
CLK
LATA
GN
D
R39
1kΩ
R41
1kΩ
R11
50Ω
C40
0.1µ
FJ3 GN
D
ENC
OD
E A
VDL
R44
1kΩ
R42
00Ω
R43
00Ω
C25
0.1µ
F
E13
E14
E12 VD
L
E15
GN
D
GN
D
R46
1kΩ
R47
1kΩ
R9
00Ω
DR
A
R10
00Ω
U6
74LC
X86
**D
UT
CLO
CK
SEL
ECTA
BLE
****
TO B
E D
IREC
T O
R B
UFF
ERED
**
DR
B
R12
00Ω
4B13
1B2
VCC
141A
1
3Y8
3A9
3B10
4Y11
4A12
GN
D 2Y 2B 2A 1Y
7 6 5 4 3
U5
74LC
X86
ENC
XB
GN
D
VDL
TIEB
GN
D
R52
1kΩ
R54
1kΩ
R50
51Ω
C42
0.1µ
FJ2 GN
D
ENC
OD
E B
ENC
XBEN
CB
R53
00Ω
R50
00Ω
E36
E35
GN
D
GN
D
GN
D
VDL
VDL
R49
1kΩ
C41
0.1µ
F
VDL
E34
E37
E16 VD
L
E38
GN
D
GN
D
R48
1kΩ
R55
1kΩ
CLK
LATB
R13
00Ω
**D
UT
CLO
CK
SEL
ECTA
BLE
****
TO B
E D
IREC
T O
R B
UFF
ERED
**
J5 GN
DR
1450
Ω
GN
D
R20
00Ω
R40
00Ω
TIEA
TIEB
ENC
AEN
CB
R8
00Ω
TO T
IE C
LOC
KS
TOG
ETH
ER
GN
D
REF
INB
C24
0.1µ
F
GN
D
REF
INA
C27
0.1µ
F
T1
Figure 26. PCB Schematic
AD9288
Rev. C | Page 18 of 24
00585-027
D9A
1
D8A
2
D7A
3
D6A
4
D5A
5
D9M
D8M
D7M
D6M
D5M
20 19 18 17 16
D4A
6
D3A
7
D2A
8
D1A
9
D0A
10
D4M
D3M
D2M
D1M
D0M
15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
U7
CTS
20VA
LUE
= 50
P3H
EAD
ER40
D9X
1
D8X
2
D7X
3
D6X
4
D5X
5
D9P
D8P
D7P
D6P
D5P
20 19 18 17 16
D4X
6
D3X
7
D2X
8
D1X
9
D0X
10
D4P
D3P
D2P
D1P
D0P
15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
U9
CTS
20VA
LUE
= 50
40 38 36 34 32
GN
D
DR
AG
ND
D9P
D8P
39 37 35 33 31
30 28 26 24 22
D7P
D6P
D5P
D4P
D3P
29 27 25 23 21
20 18 16 14 12
D2P
D1P
D0P
GN
D
GN
D
19 17 15 13 11
10 8 6 4
GN
D
2
GN
D
GN
DG
ND
GN
DG
ND
9 7 5 3 1
40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
D0M
11
GN
D12
D0X
CLK
LATA
14 13
GN
D1
D9M
2
D8M
3
D7M
4
D6M
5
VDL
D9X
D8X
D7X
D6X
24 23 22 21 20
D5M
6
D4M
7
D3M
8
D2M
9
D1M
10
D5X
D4X
D3X
D2X
D1X
19 18 17 16 15
OE
X0 X1 X2 X3 X4 X5 X6 X7 X8
VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
X9Y9
GN
DC
LK
U2
74LC
X821
C21
0.1µ
F
GN
D
+IN
8
NC
7
V–6
–OU
T5
–IN
VOC
M V++O
UT
1 2 3 4
R16
525Ω
R17
500Ω
AD
8138
AM
POU
TAA
MPO
UTA
B
U11
AM
PIN
A
R18
500Ω
R15
500Ω
R19
4kΩ
R21
1kΩ
GN
D
GN
D
GN
D
+5V
+5V
C32
0.1µ
FC
330.
1µF
R22
50Ω
R23
50Ω
–5V
C2
15pF
OPA
MP
INPU
T O
FF P
IN O
NE
OF
TRA
NSF
OR
MER
D0B
1
D1B
2
D2B
3
D3B
4
D4B
5
D0N
D1N
D2N
D3N
D4N
20 19 18 17 16
D5B
6
D6B
7
D7B
8
D8B
9
D9B
10
D5N
D6N
D7N
D8N
D9N
15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
U8
CTS
20VA
LUE
= 50
P2H
EAD
ER40
D0Y
1
D1Y
2
D2Y
3
D3Y
4
D4Y
5
D0Q
D1Q
D2Q
D3Q
D4Q
20 19 18 17 16
D5Y
6
D6Y
7
D7Y
8
D8Y
9
D9Y
10
D5Q
D6Q
D7Q
D8Q
D9Q
15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
U10
CTS
20VA
LUE
= 50
40 38 36 34 32
GN
D
DR
BG
ND
D9Q
D8Q
39 37 35 33 31
30 28 26 24 22
D7Q
D6Q
D5Q
D4Q
D3Q
29 27 25 23 21
20 18 16 14 12
D2Q
D1Q
D0Q
GN
D
GN
D
19 17 15 13 11
10 8 6 4
GN
D
2
GN
D
GN
DG
ND
GN
DG
ND
9 7 5 3 1
40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
D9N
11
GN
D12
D9Y
CLK
LATB
14 13
GN
D1
D0N
2
D1N
3
D2N
4
D3N
5
VDL
D0Y
D1Y
D2Y
D3Y
24 23 22 21 20
D4N
6
D5N
7
D6N
8
D7N
9
D8N
10
D4Y
D5Y
D6Y
D7Y
D8Y
19 18 17 16 15
OE
X0 X1 X2 X3 X4 X5 X6 X7 X8
VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
X9Y9
GN
DC
LK
U3
74LC
X821
C20
0.1µ
F
GN
D
+IN
8
NC
7
V–6
–OU
T5
–IN
VOC
M V++O
UT
1 2 3 4
R25
525Ω
R29
500Ω
AD
8138
AM
POU
TBB
AM
POU
TB
U12
AM
PIN
B
R26
500Ω
R31
500Ω
R27
4kΩ
R28
1kΩ
GN
D
GN
D
GN
D
+5V
+5V
C35
0.1µ
FC
340.
1µF
R30
50Ω
R24
50Ω
–5V
C36
15pF
Figure 27. PCB Schematic (Continued)
AD9288
Rev. C | Page 19 of 24
0058
5-02
8
Figure 28. Top Silkscreen
0058
5-02
9
Figure 29. Top Routing
0058
5-03
0
Figure 30. Ground Plane
0058
5-03
1
Figure 31. Split Power Plane
0058
5-03
2
Figure 32. Bottom Routing
0058
5-03
3
Figure 33. Bottom Silkscreen
AD9288
Rev. C | Page 20 of 24
TROUBLESHOOTING If the board does not seem to be working correctly, try the following:
• Verify power at the IC pins.
• Check that all jumpers are in the correct position for the desired mode of operation.
• Verify that VREF is at 1.23 V.
• Try running Encode clock and analog inputs at low speeds (20 MSPS/1 MHz) and monitor LCX821 outputs, DAC outputs, and ADC outputs for toggling.
The AD9218/AD9288 evaluation board is provided as a design example for customers of Analog Devices, Inc. ADI makes no warranties, express, statutory, or implied, regarding merchantability or fitness for a particular purpose.
AD9288
Rev. C | Page 21 of 24
OUTLINE DIMENSIONS
TOP VIEW(PINS DOWN)
1
1213
2524
363748
0.270.220.17
0.50BSC
7.00BSC SQ
SEATINGPLANE
1.60MAX
0.750.600.45
VIEW A
9.00 BSCSQ
PIN 1
0.200.09
1.451.401.35
0.08 MAXCOPLANARITY
VIEW AROTATED 90° CCW
SEATINGPLANE
10°6°2°
7°3.5°0°0.15
0.05
COMPLIANT TO JEDEC STANDARDS MS-026BBC
Figure 34. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48)
Dimensions shown in millimeters
ORDERING GUIDE Model Temperature Range Package Description Package Options
AD9288BST-40 –40°C to +85°C 48-Lead Low Profile Quad Flat Package ST-48 AD9288BSTZ-401 –40°C to +85°C 48-Lead Low Profile Quad Flat Package ST-48 AD9288BSTZRL-401 –40°C to +85°C 48-Lead Low Profile Quad Flat Package ST-48 AD9288BST-80 –40°C to +85°C 48-Lead Low Profile Quad Flat Package ST-48 AD9288BSTZ-801 –40°C to +85°C 48-Lead Low Profile Quad Flat Package ST-48 AD9288BST-100 –40°C to +85°C 48-Lead Low Profile Quad Flat Package ST-48 AD9288BSTZ-1001 –40°C to +85°C 48-Lead Low Profile Quad Flat Package ST-48 AD9288/PCB Evaluation Board
1 Z = Pb-free part.
AD9288
Rev. C | Page 22 of 24
NOTES
AD9288
Rev. C | Page 23 of 24
NOTES
AD9288
Rev. C | Page 24 of 24
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00585–0–12/04(C)