3D VLSI OVERVIEW, LETI COOLCUBETM TECHNOLOGY

M. Vinet

P. Batude, C. Fenouillet-Beranger, O. Billoint, O. Rozeau,

G. Cibrario, L. Brunet, S Kerdiles, JM Hartmann, H.

Sarhan, I. Rayane, F. Deprat, A. Fustier, J-E. Michallet,

O. Faynot, O. Turkyilmaz, J-F. Christmann, S. Thuries, F.

Clermidy

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Common human sense,

When we miss space

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Common human sense,

…we pile up

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Common human sense,

Traffic jam Need for short distance

communication pathsSST 2015 April 23rd| Maud Vinet

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Context

0

5000

10000

15000

20000

0,35um 130nm 65nm 28nm 14nmProcess Node

Number of Design Rules(Extracted from PDKs)

0.00E+00

1.00E-13

2.00E-13

3.00E-13

4.00E-13

5.00E-13

6.00E-13

28nm 14nm 10nm 7nmProcess Node

Delay of a single wire of the same circuit (s)(extracted from internal DRMs)

Scaling is about to

be more and more

complex

Scaling is about to

be more and more

complex

Back End

performances are

decreasing

Back End

performances are

decreasing

TSV [1]

Size : 10x10um2

Pitch : 30um

HD-TSV [1]

Size : 0,85x0,85um2

Pitch : 1,75um

Cu-Cu [1]

Size : 1,7x1,7um2

Pitch : 2,4um

3D-VLSI (28nm) [2]

Size : 0,05x0,05um2

Pitch : 0,11umE

ne

rgy

Eff

icie

ncy

En

erg

yE

ffic

ien

cy

3D Interconnect Technology3D Interconnect Technology

[1] Patti B., « Implementing 2.5D and 3D Devices », In AIDA workshop in Roma, 2013.[2] Taken from internal Design Rules Manual

Today’s focus: fine grain 3D Physical implementationToday’s focus: fine grain 3D Physical implementation

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Agenda

CoolCubeTM

unique features

Opportunities

CoolCube TM

enablers

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Technological implementation of

3DVLSI

Bottom layer processing with

plugs down to the CMOS.

Bottom layer can be any

technology, for simplicity, in

these schematics, bulk (Finfet or

planar) technology has been

represented.

Fabrication of the inter level

metal line to ensure short

distance connexion with bottom

layer.

High quality top film transfer by

molecular bonding.

Lithographic alignment precision between tiers

P. Batude et al, VLSI 2011

CoolCubeTM technology

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CoolCubeTM contacts integration

scheme

3D contact pitch and dimensions close to planar

Δh ~ 100 nm

3D contact process similar to 2D planar W plug process

• Contact in an oxide with a slightly higher depth

• No keep out of zone

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Highest density of vias between tiers

0.01 0.1 1 10

0.01

0.1

1

10

Alig

nmen

t acc

urac

y (µ

m)

3D contact width (µm)

SOI TSV

BULK TSV

sequential

65nm node

14nm node

[C]

[A,B]

[D]

[E]

D=5.000.000/mm2

D=10.000/mm2

D=100.000/mm23D TSV

D> 100.000.000/mm 2

Sequential 3D

At 14nm node, available via density D>100 million vias/mm2

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Enablers

CoolCubeunique

features

Opportunities

CoolCube TM

enablers

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Advantages of 3D VLSI: reduction of

interconnect length

For n stacked layer the global interconnect path

may be reduced by √n

Reduction in interconnect length

• Faster circuit speed

• Reduced power consumption

Eventually lower cost

Smaller physical size

Source: H. Hua, IEEE 2006

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CMOS over CMOS

Power, performance, area, cost metric

Decreased delay and power due to shorter wirelengths

� reduced wire capacitance

� less signal buffering requirement

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3D FPGA: 14nm planar FDSOI versus

2 stacked 14 nm FDSOI levels

O. Turkylmaz et al., DATE 2014

Partitioning SRAM memory on bottom level, logic on top

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3D FPGA: 14nm planar FDSOI versus

2 stacked 14 nm FDSOI levels

1.5 node gain without scaling

O. Turkylmaz et al., DATE 2014

� Average gain benchmark

for 6 circuits/ planar

� Area gain=55%

� Perf gain = 23%

� Power gain = 12%

Energy-delay product of FPGA benchmark circuits

for 2D and 3D architectures

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CoolCube™ for high mobility channel

Opportunities

P. Batude et al., VLSI 2009

Independent process for high mobility materials

Source: T. Irisawa et al., VLSI 2013 (AIST)

EU initiative “COMPOSE3”

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CoolCube™ for heterogeneous co-

integration

Opportunities

Highly miniaturized pixels Gaz sensors (NEMS with CMOS)

� Independent optimization of each level

� Proximity between stacked functions (signal/noise ratio)

P. Coudrain et al., IEDM 2008

First step to high level of integration for interconnectivity

I. Ouerghi et al, IEDM 2015

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Agenda

CoolCubeunique

features

Opportunities

CoolCube TM

enablers

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CoolCubeTM enablers

Low resistivity 3D

connections

Local Interconnect

Level

• Thermal

stability and

low resistivity

Low thermal

budget top layer

thermal stability

Bottom MOS FET

thermal stability

High quality top

film

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High quality top film

Recristallization

techniques Molecular bonding

• Crystalline orientation

top vs bottom same independant

• Thermal budget high low

• Defect density high

supplier dependent

low

• Channel thickness

control CMP supplier dependent

• Channel material same independant

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High quality top films

L. Brunet, ECS 2014

Back side macroscopic

aspect of a 300mm wafer

Front side macroscopic

aspect of a 300mm wafer

Infrared characterization Acoustic characterization

300mm blanket Si film on top of a CMOS layer by molecular

bonding

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Low thermal budget CMOS

• Active area

patterning

• Gate oxide

• Gate stack

• Dopant activation

• Epitaxy

• Spacer deposition

450 500 550 600 650 … 800

Bottom layer and interconnection stability

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Bottom CMOS thermal stabilty

Si NMOS/SiGe EPI PMOS

Dual Epi (SiGe-B

PMOS/SiC-P NMOS)

Dual Spacer Zero

SPACER

NiPt salicidation

Standard Back-end

STI

WELL/GP implants

HfO2/Dual metal gate

Spike anneal

PMD

Contacts + W filling :CMP

Additional anneals (top

level anneal simulation)

Additional anneals (top

level anneal simulation)

1

2 BOX

N PNiPt

Si 6nm20nm BOX

N P

CNTAW

W

NiPt

Si 6nm20nm

1

2

Additional

anneal variants

Reference

no anneal

400°C 2h

450°C 2h

500°C 2h

550°C 2h

450°C 5h

500°C 5h

600°C 2min

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Bottom CMOS thermal stabilty

-8.5

-8

-7.5

-7

-6.5

-6

-5.5

-5

700 900 1100 1300 1500

Ioff

Lo

g(A

/µm

)

Ion(µA/µm)

No anneal

400°C 2h

450°C 2h

500°C 2h

550°C 2h

500°C 5h

450°C 5h

No anneal, 400°C

2h, 450°C 2h

500°C 2h

550°C 2h

NMOS After CMP PMD

Vdd 1V

Lg 30nm W=0.21µm

-8.2

-8

-7.8

-7.6

-7.4

-7.2

-7

-6.8

-6.6

-1000-900-800-700-600

Ioff

Lo

g(A

/µ

m)

Ion(µA/µm)

No anneal

400°C 2h450°C 2h

500°C 2h550°C 2h

550°C 5h450°C 5h

PMOS After CMP PMD

Vdd -1V

Lg 30nm W=0.3µm

550°C 2h

500°C 2h

450°C 2h

No

anneal,

400°C 2h

FEOL In situ doped technology stable up to 550°C 2h

• Salicide morphological thermal stability is the bottle neck

• Improvement of salicide thermal stability on going

C. Fenouillet-Beranger, ESSDERC 2014

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• Active area

patterning

• Gate oxide

• Gate stack

• Dopant activation

• Epitaxy

• Spacer deposition

450 500 550 600 650 … 800

Bottom layer and interconnection stability

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Junction activation

Duration (s)

Temperature (°C)

1000

900

800

700

600

500

10-9 10-6 10-3 1 103

Advanced laser DSA RTA Furnace

?

?

Standard technologies

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Junction activation

Duration (s)

Temperature (°C)

1000

900

800

700

600

500

10-9 10-6 10-3 1 103

Advanced laser DSA RTA Furnace

?

?

Standard technologiesCrème brûlée technique

Solid phase epitaxy regrowth

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Dopant activation by SPER

Regrowth at LT (≤ 600C)

Amorphizing implant c-Si

a-Si

a/c

interface

Deptha-Si c-Si

[Active]

Depth

BOX

BOX

EOR defects

Technique well suited to top layer on SOI (BOX sink effect)

• Less EOR defects in SOI devices due to BOX presence

• No Boron deactivation nor junction leakage increase

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Low T° junction activation

Implanted Dose (1015 x at/cm2)

5.5 5.5 3 1 1.7 1

L. Pasini et al. IWJT 2014

L. Pasini et al, IWJT 2014

Lower sheet resistance in SPER than RTA Spike annealing

Optimized dose wrt

clusterization

Sh

ee

tre

sist

an

ce(a

u)

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Thermal budget management

• Active area

patterning

• Gate oxide

• Gate stack

• Dopant activation

• Epitaxy

• Spacer deposition

450 500 550 600 650 … 800

Bottom layer and interconnection stability

EOT reduction

Harness the energy of the technology mainstream momentum

Junction control

Thin film management

Low k

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Low resistivity thermally stable

interconnects: W and SiO2

Learning from the others

ρW(5.3 μΩ.cm) = 3 ρCu

(1.7 μΩ.cm)

ρW is predicted to cross below

that for Cu at linewidths below

25 nm.Micron 110nm eDRAM technology

Source: F. Fishburn et al., VLSI 2003

FEOL � MEOL � FEOL

Contamination protocole

Low resistivity tungsten

Source: D.Choi et al, JVSTA 2011

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Key messages

• CoolCube TM is a powerful alternative to

2D scaling

• Path for high mobility materials co-integration

• Paves the way for heterogeneous integration

• Key technological steps are tackled

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What’s next?

50% Area

reduction

50% Area

reduction

3D Clock Tree3D Clock Tree

Full 3D Routing

in one run with

Timing Closure

Full 3D Routing

in one run with

Timing Closure

Inter-Tier Power

Supply

Distribution

Inter-Tier Power

Supply

Distribution

Tier-Specific

Process Corner

Specification

Tier-Specific

Process Corner

Specification

Single Tool

Methodology

Single Tool

Methodology

ENABLING 3D-VLSI

Tier-to-Tier Cell

Placement

Optimization

Tier-to-Tier Cell

Placement

Optimization

Power

Optimization

Power

Optimization

I/Os and

ESDs

I/Os and

ESDs

…etc…etc

Olivier Billoint et al, DATE 2015

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What’s next?

50% Area

reduction

50% Area

reduction

3D Clock Tree3D Clock Tree

Full 3D Routing

in one run with

Timing Closure

Full 3D Routing

in one run with

Timing Closure

Inter-Tier Power

Supply

Distribution

Inter-Tier Power

Supply

Distribution

Tier-Specific

Process Corner

Specification

Tier-Specific

Process Corner

Specification

Single Tool

Methodology

Single Tool

Methodology

ENABLING 3D-VLSI

Tier-to-Tier Cell

Placement

Optimization

Tier-to-Tier Cell

Placement

Optimization

Power

Optimization

Power

Optimization

I/Os and

ESDs

I/Os and

ESDs

…etc…etc

Olivier Billoint et al, DATE 2015

SK Lim, Georgia Tech, MINOS 2015

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What’s next?

50% Area

reduction

50% Area

reduction

3D Clock Tree3D Clock Tree

Full 3D Routing

in one run with

Timing Closure

Full 3D Routing

in one run with

Timing Closure

Inter-Tier Power

Supply

Distribution

Inter-Tier Power

Supply

Distribution

Tier-Specific

Process Corner

Specification

Tier-Specific

Process Corner

Specification

Single Tool

Methodology

Single Tool

Methodology

ENABLING 3D-VLSI

Tier-to-Tier Cell

Placement

Optimization

Tier-to-Tier Cell

Placement

Optimization

Power

Optimization

Power

Optimization

I/Os and

ESDs

I/Os and

ESDs

…etc…etc

Olivier Billoint et al, DATE 2015

SK Lim, Georgia Tech, MINOS 2015

• CAO tools

• Design enablement

• IP building blocks

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Thank you for your attention