32-bit Pipelined RISC Processor

Group 1Group 1aka “Go Us”aka “Go Us”

Alice WangAnn HoJason Fong

CS m152bTA: Young ChoLab section 1

General Review of a Pipelined Processor

Instruction Memory

Register File ALU

Data Memory

PC Control

IF/ID ID/EX EX/MEM MEM/WB

Memory Controller Design

Design challenge: 32-bit processor with 16-bit memory interface• One every memory access, need to make two memory accesses in

order to get a 32-bit word out of a 16-bit memory interface.

Solution: Clock memory controller twice as fast as rest of processor• Effectively makes a memory access on the rising and falling edge of

the processor’s clock cycle• Each processor clock cycle corresponds to two clock cycles of the

memory controller• This allows two memory accesses per processor clock cycle

Instruction Format

31 28 27 25 24 22 21 19 8 4 3 0

31 28 27 25 24 22 15 0

31 28 15 0

R-type instruction

I-type instruction

J-type instruction

opcode rs rt rd shamt funct

opcode rs rt imm16

opcode imm16

Multiplier

0 • • • 3 2 - b i t v a l u e • • • 0 0 0 0 0 0 0 0 0 0 0

Parallel Multiplier(more efficient, but more hardware)

x4 x3 x2 x1 x0

z9 z8 z7 z6 z5 z4 z3 z2 z1 z0

Data Forwarding

ID/EX EX/MEM MEM/WB

Forward From ALU output

Forward From memory output

Hardware NOP Insertion

PC Adder

Hold PC value

Insert NOP

Data Forwarding and Stall Insertions:Observed Results

Sample program: Bubble-sort 6 numbers

Assembler insertion of NOPs for data hazards and branch/jump delays

Machine code size: 66 words of memory

Execution time: ~750 clock cycles

Hardware data forwarding and stall insertion:

Machine code size: 35 words of memory

Execution time: ~400 clock cycles

Conclusion

Still cooking something up…

We conclude that we do not know what to conclude.

References

• Hennessey and Patterson, Computer Organization and Design (2nd Ed.), 1998, pages 476-495

• Donaldson, John L., “Pipeline Hazards”, http://occs.cs.oberlin.edu/faculty/jdonalds/317/lecture08.html

• Ercegovac, Intro To Digital Systems

• Add stuff about assembler

32-bit Pipelined RISC Processor

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