2.1 Introduction 2.2 Basic Process Steps 2.3 CMOS...

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Transcript of 2.1 Introduction 2.2 Basic Process Steps 2.3 CMOS...

Chapter 2 Fabrication of Chapter 2 Fabrication of MOSFETsMOSFETs

2.1 Introduction2.2 Basic Process Steps2.3 CMOS Fabrication Process Flow2.4 Layout Design Rules

2.1 Introduction2.1 Introduction

CMOS technologies Planarized semiconductor process technology Provide both NMOS and PMOS devices in one process flow Process all devices of the same kind simultaneously Cost is proportional to the device size rather than the number of devices Transistors are fabricated on Si substrate followed by metal interconnections Existing CMOS technologies: n-well process p-well process Twin-well process Triple-well process

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2.2 Basic Process Steps

Oxidation Formation of silicon dioxide layer on the surface of Si wafer Dry oxidation: lower rate and higher quality Wet oxidation: higher rate and lower quality

Deposition Formation a thin film on the surface of Si wafer Thin film materials: semiconductor, insulator and metal Typical chemical vapor deposition methods: APCVD, LPCVD and PECVD

Implantation/diffusion Process steps to specify the doping species and concentration Ion implantation: dopants are vaporized, accelecrated and directed at a Si substrate Diffusion: dopants diffuse from a high-concentration source into Si substrate

Etch Removal of specific material layers on the Si substrate Classified as dry and wet etch

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Photolithography Uniformly covers of the substrate with photoresist Selectively exposes with a mask Develops the photoresist to define the desirable patterns Suitable for pattern definition with small feature sizes

Isolation Isolation is required from one active area to another Typical isolation is provided by a thick oxide layer (field oxide) Parasitic channel should be prevented under the field oxide Local oxideation of silicon (LOCOS) technique

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2.3 CMOS Process Flow

Process flow of a n-well CMOS technology

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2.4 Layout Design Rules

Layout rules Layout rules are given for each one of the layers in creating masks Designers have to follow the rules for circuit layout

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Layout of MOS transistors

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Layout of a CMOS inverter

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