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conventionally used in most designs over the last
decade.The previous designs of the four transistors and
three transistors are shown in figure1.The proposed twotransistor XOR gates can be designed using general
logic implementation. The design[15] of a two transistor
XOR gate is shown in figure 2.
The circuite operation is as follows when A=0 andB=0 both the pmos transistors are ON and it will
produce the output is low.when either one of thetransistor is ON it Produces output as high, when A=1
and B=1 both the pmos transistors are OFF and it will
produce the output is low.
Fig.1(a) Fig.1(b)
Fig.1(c) Fig.1(d)
Fig.1(e)
Fig.1: Previous designs of 4-T and 3-T XOR gates.
Fig.2: Proposed Design of 2T -XOR.
III. DESIGN OF THE SIX-TRANSISTOR FULL
ADDER
The new design of full adders[7][11] which forms the
basic building blocks of all digital VLSI circuits hasbeen undergoing a considerable improvement, being
motivated by three basic design goals, viz. minimizing
the transistor count, minimizing the power consumption
and increasing the speed.
Conventional Static[3] CMOS full adder: The
conventional CMOS logic gate full adder[16] is shown as
Fig. 2 while the equation of a full adder are present as
equation(1) - (4) [7].
x + y + Cin =2Cout + Sum -------------------(3)
Cout =(y(x y)) + (Cin(x y)) -----------(4)
Sum = x y Cin -----------------------(5)
The static CMOS Full adder is implemented by using
26 transistors.we can also minimize the number of
transistors by using the CMOS Transmission gate andCMOS inverter.With this logic we reduce the number of
transistors to 20.By using Pass transistor logic we can
minimize the static power dissipation and number of
transistors.Full adder is design with 14 transistors[9] byusing Pass transistor logic.which leads the moderate
power dissipation.The full adder design also
implemented by using 10 transistors[6].
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Fig.3: Previous designs of 8T Full adder.
Mainly the XOR[8] and XNOR circuits are used indesigning of full adder. In previous design the Full
adder is designed by using eight transistors.which can
dissipates more power compare to this work.In this
paper the design of full adder using two transistors xorgates can ge implemented.The Six transistor Full adder
is shown in Figure.4.
Fig.4: Proposed Design of 6TFull adder
IV. RESULTS AND DISCUSSION
The exclusive-or gate and full adder are operated at
100 MHz signal frequency. In fact, in addition to normaltransistors, circuits are tested in corner cases with fast
and slow transistors and their combinations too. The
difference in these stages is in consumption of power
and falling and rising times which are caused due to thedifference in NMOS and PMOS transistors power
consumption and speed. After the simulation, the layout
of circuit is drawn. By the post simulation result alongwith a few corrections have achieved in sizes that the
circuit has an accurate operation. Simulation results are
performed by using digital schematic design tool ofMentor graphics tool. The waveforms of proposed
design as shown in figure 5 and 6 for XOR gate and fulladder.
Fig.5: Wave forms of 2T-XOR gate.
Fig.6: Wave form of 6T-Full adder
The comparison of the different XOR gates and Full
adders are shown in table.1 according to their transistor
count and power dissipation.
Table.1: Comparison of existed full adders with
proposed one in terms of transistor count and powerdissipation
Strucures No
Transistors
Power
(w)XOR (Fig.1(a)) 4 0.499
XOR(Fig.1(b)) 4 0.486
XOR(Fig.1(c)) 4 0.140
XOR (Fig.1(d)) 4 0.434
XOR (Fig.1(e)) 3 0.435
XOR (Fig.2) 2 0.135
FULLADDER(Fig.3) 8 0.361
FULLADDER(Fig.4) 6 0.235
V. CONCLUSION
In this paper different CMOS logic design familieshas been reviewed and evaluated based on the
performance metrics like area, power, delay andtransistor count. But the previous techniques have the
disadvantages of transistor count, delay and power
dissipation. The current work proposes the design of an
6T full adder, which is by far the full adder with the
lowest transistor count. In designing the proposed 6Tfull adder, a novel 2T XOR gate has also been proposed.
The implementation of Full Adder has been presented
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and it can be extended to higher bit adders. The future
research activities may include integration of the
proposed full Adders in complex digital systems,combining sequential and combinational logic.
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[5] H. T. Bui, A. K. Al-Sheraidah, and Y.Wang, New4-transistor XOR and XNOR designs, inProc. 2nd
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[7] A. M. Shams, T. K. Darwish, and M. A. Bayoumi,
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CMOS full adder,IEEE J.Solid-State Circuits,vol. 27, no. 5, May 1992, pp. 840844.
[12] E. Abu-Shama and M. Bayoumi, A new cell for
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[14] Y. Tsividis,Mixed Analog-Digital VLSI Devices
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[15] M. Morris Mano,Digital Design, Prentice Hall ofIndia, 2nd Edition, 2000.
[16] S. Goel, M.A. Elgamel, M.A. Bayoumi, Y. Hanafy,Design Methodologies for high performance noise
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[17] Moore, Gordon E. (1965). "Cramming more
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Mr. Pakkiraiah Chakali completed his
B.Tech in Electronics and Communication
Engineering from Sreenivasa Institute of
Technology and mamagement studies,
Chittoor, Andhra Pradesh, India in 2009. he is
now pursuing his Master of Technology
(M.Tech) in VLSI at Sree Vidyanikethan
Engineering College , Tirupati, Andhra
Pradesh, India. His interest includes Digital
Desi n, ASIC Desi n, VLSI Testin .
Ms. Adilakshmi Siliveru completed her
B.Tech in Electronics and Communication
Engineering from Kandula Obula Reddy
Memorial College Of Engineering, Kadapa,
Andhra Pradesh, India in 2011. She is now
pursuing her Master of Technology (M.Tech)
in VLSI at Sree Vidyanikethan Engineering
College , Tirupati, Andhra Pradesh, India. Her
interest includes Digital Design, VLSI
Testing.
http://download.intel.com/museum/Moores_Law/Articles-Press_Releases/Gordon_Moore_1965_Article.pdfhttp://download.intel.com/museum/Moores_Law/Articles-Press_Releases/Gordon_Moore_1965_Article.pdfhttp://en.wikipedia.org/wiki/Electronics_%28magazine%29http://en.wikipedia.org/wiki/Electronics_%28magazine%29http://download.intel.com/museum/Moores_Law/Articles-Press_Releases/Gordon_Moore_1965_Article.pdfhttp://download.intel.com/museum/Moores_Law/Articles-Press_Releases/Gordon_Moore_1965_Article.pdf7/27/2019 119-449-1-PB
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Ms. Neelima Koppala, M.Tech., is currently
working as an Assistant Professor in ECE
department of Sree Vidyanikethan
Engineering College, Tirupati. She hascompleted M.Tech in VLSI Design, from
Satyabhama University. Her research areas are
RFIC Design, Digital Design, Low Power
VLSI Design and VLSI Signal Processing.