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San Jose State UniversityDepartment of Electrical Engineering

EE 166 ProjectSpring 2003

Phase Frequency Detector (PFD)

Prof. David Parent

Group Members: Marcella GrantRobert ShenHan DuongJeremiah Martin

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OUTLINE

Introduction Specifications Design Flow Results Conclusion

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What is a PFD?

Component used in a PLL that compares two signals.Evaluates Phase and Frequency The output voltage gives the information of the phase and frequency differences of two signals.

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Specifications

Process: AMI06Frequency: ≥ 200 MHzPower: ≤ .25 WattsDuty Cycle: 50%VDD: 5 VInputs: 2Outputs: 2

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Schematic of PFDPFD Charge

Pump/LPF VCO

%N

OUTPUTINPUT

PLL

Q

QSET

CLR

D

Q

QSET

CLR

D

UP

DOWN

INPUT

FEEDBACK

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Design Flow

PostExtractionSimulation

Verification

DesignComplete

Testbench

HandCalculations

SchematicCapture

Layout

DRCCircuit

ExtractionLVS

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Transistor Level of PFD

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Test Bench

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Layout View

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LVS Report

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Transient Analysis

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DC Analysis

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Results

Parameters Specifications Design Results Meet Specs.?

Frequency ≥ 200 MHz 333 MHz Power ≤ .25 Watts 2mW Duty Cycle 50% 50% VDD 5V 5V Prop. Delay ≤ 5ns .5ns

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Conclusion

Successfully Designed and Implemented PFD for our PLL project.Met all Specifications.