Post on 31-Mar-2015
1
Electrical Engineering 2
Microelectronics 2
Dr. Peter Ewen
(Room G08, SMC; email - pjse)
Lecture 13
2
The Abrupt Junction
ND
Do
pan
t co
nce
ntr
atio
n N
A o
r N
DDiffusion
Implantation
p n
Depth into wafer, x
xj
ABRUPT JUNCTION
Abrupt junctionmodelNA
Do
pan
t co
nce
ntr
atio
n N
A o
r N
D
Depth into wafer, x
ND
LINEARLY-GRADEDJUNCTION
xj
p n
3
-
--
--
--
--
-+
++
+
+
+
+
+ +
+
+ -
--
-
-
-
-
- -
-+
+
+
+
+
+
+
++
-
--
--
--
--
-+
++
+
+
+
+
+ +
+
+ -
--
-
-
-
-
- -
-+
+
+
+
+
+
+
++
p-type n-type
-ve +ve
junction
depletionregion
EThe charges in the depletion region are those on the carriers and on the charged impurity ions fixed in the lattice.
Taking the sign of the charges into account:
c = e(p – n + ND – NA)
= (p – n + ND – NA)dE edx
For simplicity take n = 0 & p = 0 – the depletion approximation
4
-
--
--
--
--
-+
++
+
+
+
+
+ +
+
+ -
--
-
-
-
-
- -
-+
+
+
+
+
+
+
++
-
--
--
--
--
-+
++
+
+
+
+
+ +
+
+ -
--
-
-
-
-
- -
-+
+
+
+
+
+
+
++
p-type n-type
Ch
arg
ed
en
sit
y,
c
-eNA
Distance, x
eND
lp x=0 ln
0
Depletionregion
Fig. 76.2
junction
Charge density variation through a pn junction
5
To find the Electric Field For the p-type side we have:
)( pAp
pA
Ap
Ap
Ap
lxNe
E
lNe
C
CxNe
E
dxNe
E
Ne
dx
dE
Poisson’s equation on
p-type side
Since NA is constant (abrupt junction)
Since E = 0 outside the depletion region, i.e. at x Ip
Similarly, for the n-type side: )( nDn lxNe
E
6
To find the Potential
For the p-type side we have:
'2
)2
(
)(
Cxlx
Ne
V
dxlxNe
V
dxEV
dx
dVE
pAp
pAp
pp
pp
The electric field, E, is defined by:dx
dVE
)( pAp lxNe
E
If we take the zero of potential to be at x = 0 then C' = 0.
7
-
--
--
--
--
-+
++
+
+
+
+
+ +
+
+ -
--
-
-
-
-
- -
-+
+
+
+
+
+
+
++
-
--
--
--
--
-+
++
+
+
+
+
+ +
+
+ -
--
-
-
-
-
- -
-+
+
+
+
+
+
+
++
p-type n-type
Po
ten
tia
l, V
Distance, x
VB
Vp
Vn
Ele
ctr
ic
fie
ld, E
Distance, xEmax
Ep En
Ch
arg
ed
en
sit
y,
c
-eNA
Distance, x
eND
0
0
0
lp x=0 ln
E
8
MOS Transistor – Basic Structure
Fig. 80
n+ n+
Channel
SiO2
SourceGate
Drain
+Vg
n-channeldevice
MetalOxideSemiconductor
p-type substrate
9
LECTURE 13
Operation of the MOS transistor – gate-controlled surface effects
MOS fabrication – enhancement and depletion devices
MOS Pinch-off
10
p-typesubstrate
drain
source
gate
SiO2
metaln+
n+
Ch
arg
e −ve voltageon gate
QG
QA (A ≡ Accumulation)QA = -QG
QG
QD
+ve voltageon gate
Channel forms when the +ve voltage onthe gate is greater
than VT
(threshold voltage)
QC
(D ≡ Depletion)QD = -QG
(C ≡ Channel)QC +
n-channel device(enhancement)
Gate-ControlledSurface effects
Fig. 81
“Inversion” occurs
Distance
++
+
+
+
+
--
--
--
--
--
--
-
+
-holes
acceptor ions
electrons
11
n-typesubstrate
drain
source
gate
SiO2 p+
p+
Ch
arg
e -ve voltageon gate with magnitude
greater than VT
p-channel device
Gate-ControlledSurface effects
Fig. 82
QC
QD
QG
metal
Distance
12
1.MOS Threshold Voltage
An n-channel polysilicon gate MOS transistor has the following features:
oxide thickness tox = 0.1 mchannel width W = 18 mchannel length L = 6 msubstrate doping NA = 5x1022 m-3
oxide relative permittivity ox = 4EF − EV for substrate = 0.175 eVEg = 1.1 eV for Si
(a) Determine the gate capacitance, Cg.
(b) If the depth of the depletion region at VG = VT is0.14 m, how much of VT goes to creating QD?
13
1. MOS threshold voltage
pF
t
WLd
WL
d
A
d
ACa
ox
oxo
oxooxog
038.0101.0
106101841085.8
)(
6
6612
(a) Determine the gate capacitance, Cg.
n+
SiO2GateGate
SourceSource DrainDrainn+ n+
SiO2
SourceSource DrainDrainn+ n+
SiO2conductor (metal)insulator (oxide)conductor (silicon)
SourceSource DrainDrainn+
W L
tox
oxide thickness tox = 0.1 mchannel width W = 18 mchannel length L = 6 msubstrate doping NA = 5x1022 m-3
oxide relative permittivity ox = 4EF − EV for substrate = 0.175 eVEg = 1.1 eV for Si
14
(b) If the depth of the depletion region at VG = VT is 0.14 m, how much of VT goes to creating QD?
GateVT
SiO2
+ve
__
__ _
___
___
_ _
_ _
__
_ _ __
_ _ _ __
___
ionised acceptor atoms
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ inversion layer of electronsdepletion region
p-type substrate
Gate region of n-channel MOS
g
D
g
C
g
DCT
CT
g
C
Q
C
Q
C
QQV
QQV
CCC
QV
D
:hence , is gate under the charge the,at forms channel When the
,capacitor"" gate MOSFor . capacitor, aFor
oxide thickness tox = 0.1 mchannel width W = 18 mchannel length L = 6 msubstrate doping NA = 5x1022 m-3
oxide relative permittivity ox = 4EF − EV for substrate = 0.175 eVEg = 1.1 eV for Si
15
The part of VT that goes into creating the depletion charge QD
is therefore
V
C
eWLN
C
QV
g
A
g
D
2.310038.0
106.11014.01061018105
)1014.0(
12
1966622
6
Gate VTSiO2
+ve
__
__ _
___
___
_ _
_ _
__
_ _ __
_ _ _ __
___
p-type substrate
Gate region of n-channel MOS
__
__
LW
Depth
depth of depletion region – 0.14 m
oxide thickness tox = 0.1 mchannel width W = 18 mchannel length L = 6 msubstrate doping NA = 5x1022 m-3
oxide relative permittivity ox = 4EF − EV for substrate = 0.175 eVEg = 1.1 eV for Si
16
C.B.
V.B.
EC
EV
1.1eV
n-channel
(c) If effective inversion occurs when the channel is as n-type as the wafer is p-type, determine an approximate value for VT.
C.B.
V.B.
EC
EF
EV
1.1eV
0.175eV
p-type substrateC.B.
V.B.
EC
EF
EV
1.1eV
0.175eV
n-channel
For effective inversion EF must be 0.175eV below EC in the n-type channel, i.e. the band diagram must move down by:
(1.1 – 20.175)eV = 0.75eV.
(1.1 – 20.175)eV = 0.75eV
17
What voltage must be applied to the gate to achieve this?
V95.32.375.0 Hence
75.075.0
TV
Ve
eeV
q
EV
VqE
18
p-type substrate (wafer)NA ~ 1020 m-3
SiO2
polycrystalline Si (“polysilicon”)
donor diffusion
“self-aligned”gate
n+ n+
MOS Fabrication
n-channel enhancement device
Fig. 83
AlAl
Polysilicon GateSource Drain
n+ → “+” indicatesheavy doping
19
n+ n+
SiO2
Source
Gate contact made here
Drain
Gate Contact
Fig. 84
n-channeldevice
20
p-type substrate (wafer)NA ~ 1020 m-3
SiO2 n+ n+
MOS Fabrication
n-channel depletion device
AlAl
Polysilicon GateSource Drain
Implanted channel
21
n-channel enhancement device
n+ n+AlAl
Implanted channel
n+ n+AlAl
Polysilicon GateSource Drain
n-channel depletion device
Polysilicon GateSource Drain
VT VGS
IDS
VT VGS
IDS
0 0
Same considerations apply to p-channel devices.
22
n-channel enhancement device
MOS Pinch-off Fig. 85
sourcegate
drain
+8V 0V +7V
p-type substrate
inversion layer
n+ n+
VT = 1 V
SiO2
Vox ≥ VT everywhere between source and drain.
+7.5V
Vox drops below VT at drain end – channel becomesinterrupted or “pinched off”
depletionregion
-eE→
23
n-channel enhancement device
Condition for pinch-off Fig. 86
source
gate
drain
+8V 0V +7V
n+ n+
VT = 1 V
SiO2
7.5V
Vox is smallest at the drain end of the gate, hence pinch-off first occurs when VGD = VT
VGDVGS
VDS
VGS
VDS
VGD
G
S
D
Pinch-off first appears when: VDS = VGS – VT
VGD = VT VGS – VDS = VT VDS = VGS – VT
24
n-channel device
Condition for pinch-off – all devices
drain
n+
VGS
VDS
VGD
G
S
D
VGD = VGS – VDS n+
gate
p-channel device
VGD < VT
h VGS – VDS < VT
VDS > VGS – VT
VT +vedrain
n+
VGD
n+
gate
VT -ve
The channel will be pinched-off if the voltage difference across the oxide layer at the drain end of the channel (i.e. VGD) is less than VT
The channel will be pinched-off if the voltage difference across the oxide layer at the drain end of the channel (i.e. VGD) is greater than VT
VGD > VT
h VGS – VDS > VT
VDS < VGS – VT
25
n-channel enhancement device
Conditions for pinch-off – all devices
The channel will be pinched-off if:
n-channel depletion deviceVDS > VGS – VT
VDS < VGS – VT
p-channel enhancement device
p-channel depletion device
n-channel enhancement
device
n-channel depletion
device
p-channel enhancement
device
p-channel depletion
device
VDS +ve +ve -ve -ve
VGS +ve +ve or -ve -ve -ve or +ve
VT +ve -ve -ve +ve
26
ID
VDSVDS=VGS-VT
VDS>VGS-VT
Effect of pinch-off on the current through the device
sourcegate
drain
n+ n+
sourcegate
drain
n+ n+
27
2. Pinch-off
The terminal voltages for an n-channel enhancement MOS transistor with VT = 1V are given below. Is the channel pinched off?
VG = 5V VD = 4.5V
VS = 3V
28
VGS – VT = 1, hence VDS > VGS – VT and so the channel is pinched off.
To see if the channel is pinched off we need to compareVDS with VGS – VT . Device is n-channel so if
VDS > VGS – VT the channel is pinched offVDS < VGS – VT the channel is not pinched off
source gate drain
+5V 3V +7V
n+ n+
VT = 1 V 4.5V
VGS
VDS
VDS is the voltage on the drain with respect to the source:VDS = VD – VS = 4.5 – 3 = 1.5V
VGS is the voltage on the gate with respect to the source:VGS = VG – VS = 5 – 3 = 2V
29
Summary
MOS OPERATION
n-channel device:• VG ≤ 0 – no conduction between source and drain possible because one of the two pn junctions around source and drain is reverse biased.
• 0 < VG < VT – mobile holes repelled from surface below gate. (VT is the Threshold Voltage.)
• VG > VT – electrons attracted to surface below gate, surface inverted to become n-type, conduction between source and drain.
p-typesubstrate
source
gate
SiO2
metaln+
n+
n-channel device(enhancement)
30
MOS FABRICATION
n-channel device:
• Lightly-doped p-type wafer• Grow thin SiO2 layer for gate insulation• Deposit polycrystalline silicon for gate
electrode• Diffuse/implant n-type dopant for source and
drain (n+)• Make metal contacts – (gate contact offset)
pp--type substrate (wafer)type substrate (wafer)NNAA ~ 10~ 102020 mm--33
SiOSiO22nn++ nn++
AlAlAlAl
Polysilicon GatePolysilicon GateSource DrainSource Drain
pp--type substrate (wafer)type substrate (wafer)NNAA ~ 10~ 102020 mm--33
SiOSiO22nn++ nn++
AlAlAlAl
Polysilicon GatePolysilicon GateSource DrainSource Drain
31
ENHANCEMENT AND DEPLETION MOSFET’s
Enhancement device – no channel between source and drain for VGS = 0
Depletion device – channel deliberately created between source and drain during fabrication.
Hence there are 4 MOSFET types:
n-channel enhancementn-channel depletionp-channel enhancementp-channel depletion
nn--channel enhancement devicechannel enhancement device
nn++ nn++AlAlAlAl
Implanted channelImplanted channel
nn++ nn++AlAlAlAl
Polysilicon GatePolysilicon GateSource DrainSource Drain
nn--channel depletion devicechannel depletion device
Polysilicon GatePolysilicon GateSource DrainSource Drain
nn--channel enhancement devicechannel enhancement device
nn++ nn++AlAlAlAl
Implanted channelImplanted channel
nn++ nn++AlAlAlAl
Polysilicon GatePolysilicon GateSource DrainSource Drain
nn--channel depletion devicechannel depletion device
Polysilicon GatePolysilicon GateSource DrainSource Drain
32
MOS PINCH-OFF
Channel between source and drain becomes pinched off (i.e. interrupted) when:
VDS ≥ VGS – VT
sourcesource gategatedraindrain
nn++ nn++
sourcesource gategatedraindrain
nn++ nn++
ID
VDSVDS=VGS-VT
VDS>VGS-VT