Post on 27-Mar-2015
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Chapter 4
Computing Platforms
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Figure 4.1 Hardware architecture of a typical computing platform.
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Figure 4.2 Software layer diagram for an embedded system.
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Figure 4.3 Organization of a bus.
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Figure 4.4 The four-cycle handshake.
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Figure 4.5 A typical sequence diagram for bus operations.
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Figure 4.6 Timing diagram notation.
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Figure 4.7 Timing diagram for read and write on the example bus.
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Figure 4.8 A wait state on a read operation.
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Figure 4.9 A burst read transaction.
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Figure 4.10 State diagrams for the bus read transaction.
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Figure 4.11 A bus with a DMA controller.
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Figure 4.12 UML sequence of system activity around a DMA transfer.
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Figure 4.13 Cyclic scheduling of a DMA request.
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Figure 4.14 A multiple bus system.
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Figure 4.15 UML state diagram of bus bridge operation.
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Figure 4.16 Elements of the ARM AMBA bus system.
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Figure 4.17 Organization of a basic memory.
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Figure 4.18 An SDRAM read operation.
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Figure 4.19 The memory controller in a computer system.
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Figure 4.20 Channels and banks in a memory system.
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Figure 4.21 A BeagleBoard.
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Figure 4.22 An ARM evaluation module.
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Figure 4.23 Connecting a host and target system.
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Figure 4.24 Architecture of a logic analyzer.
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Figure 4.25 Use case for playing multimedia.
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Figure 4.26 Use case of synchronizing with a host system.
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Figure 4.27 Hardware architecture of a generic consumer electronics device.
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Figure 4.28 Platform-level data flows and performance.
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Figure 4.29 Times and data volumes in a basic bus transfer.
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Figure 4.30 Times and data volumes in a burst bus transfer.
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Figure 4.31 Memory aspect ratios.
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Figure 4.32 Front panel of the alarm clock.
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Figure 4.33 Class diagram for the alarm clock.
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Figure 4.34 Details of user interface classes for the alarm clock.
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Figure 4.35 The Mechanism class.
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Figure 4.36 State diagram for update-time.
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Figure 4.37 State diagram for scan-keyboard.
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Figure 4.38 Preprocessing button inputs.
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Figure 4.39 MPEG Layer 1 encoder.
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Figure 4.40 MPEG Layer 1 data frame format.
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Figure 4.41 MPEG Layer 1 decoder.
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Figure 4.42 Requirements for the audio player.
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Figure 4.43 Classes in the audio player.
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Figure 4.44 State diagram for file display and selection.
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Figure 4.45 State diagram for audio playback.
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Figure 4.46 Architecture of a Cirrus audio processor for CD/MP3 players.
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UN Figure 4.1
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UN Figure 4.2
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UN Figure 4.3
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UN Figure4.4
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UN Figure 4.5
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UN Figure 4.6