Post on 27-Mar-2015
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Chapter 3
CPUs
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Figure 3.1 Structure of a typical I/O device.
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Figure 3.2 The interrupt mechanism.
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Figure 3.3 Prioritized device interrupts.
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Figure 3.4 Using polling to share an interrupt over several devices.
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Figure 3.5 Interrupt vectors.
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Figure 3.6 The cache in the memory system.
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Figure 3.7 A two-level cache system.
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Figure 3.8 A direct-mapped cache.
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Figure 3.9 A set-associative cache.
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Figure 3.10 A virtually addressed memory system.
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Figure 3.11 Segments and pages.
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Figure 3.12 Address translation for a segment.
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Figure 3.13 Address translation for a page.
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Figure 3.14 Alternative schemes for organizing page tables.
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Figure 3.15 ARM two-stage address translation.
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Figure 3.16 Pipelined execution of ARM instructions.
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Figure 3.17 Pipelined execution of multicycle ARM instructions.
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Figure 3.18 Pipelined execution of a branch in ARM.
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Figure 3.19 A power state machine for a processor.
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Figure 3.20 UML collaboration diagram for the data compressor.
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Figure 3.21 Definition of the data-compressor class.
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Figure 3.22 Additional class definitions for the data compressor.
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Figure 3.23 Relationships between classes in the data compressor.
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Figure 3.24 State diagram for encode behavior.
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Figure 3.25 State diagram for insert behavior.
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Figure 3.26 A test of the encoder.
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UN Figure 3.1
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UN Figure 3.2
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UN Figure 3.3
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UN Figure 3.4
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UN Figure 3.5
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UN Figure 3.6
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UN Figure 3.7
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UN Figure 3.8
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UN Figure 3.9
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UN Figure 3.10
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UN Figure 3.11
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UN Figure 3.12