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COMP 4300 Computer Architecture

Datapath

Dr. Xiao Qin

Auburn Universityhttp://www.eng.auburn.edu/~xqin

xqin@auburn.edu

Fall, 2010

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Datapath for Branch Instructions

beq rs, rt, offsetif (R[rs] == R[rt]) then PC ← PC+4 + s_extend(offset<<2)

op rs rt offset/immediate

5 5

16

RD1

RD2

RN1 RN2 WN

WD

RegWrite

Register File

Operation

ALU

EXTND

16 32

Zero

ADD

<<2

PC +4 from instruction datapath

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Datapath: More Detailed View

4

PC

Instructionaddress

Instruction

Instructionmemory

Add Sum

a. Instruction memory b. Program counter c. Adder

AddressReaddata

Datamemory

a. Data memory unit

Writedata

MemRead

MemWrite

b. Sign-extension unit

Signextend

16 32

Simple Implementation• Include the functional units we need for

each instruction

Readregister 1

Readregister 2

Writeregister

WriteData

Registers ALUData

Data

Zero

ALUresult

RegWrite

a. Registers b. ALU

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5

5

Registernumbers

Readdata 1

Readdata 2

ALU operation4

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RTL Code for MIPS add1. Fetch

Instruction = ROM[PC], PC=PC+4

2. Read OperandsALUOp1 = Registers[rs-value],

ALUOp2 = Registers[rt-value]

3. AddALUOut = ALUOp1+ALUOp2

4. Write ResultRegisters[rd-value] = ALUOut

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Datapath Components for MIPS add

add R1, R2, R3

PC

address Inst.

R1

R2

R3

Add (control signals)

ReadRegister#1

ReadRegister#2

WriteRegister

DataPort#1

Port#2

ALU

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Datapath Connections for MIPS add

add R1, R2, R3

PC

address Inst.

R1

R2

R3

add

ReadRegister#1

ReadRegister#2

WriteRegister

DataPort#1

Port#2

ALU

CLK

InterconnectionsWhat is missing?

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Critical Path for MIPS add

add R1, R2, R3

PC

address Inst.

R1

R2

R3

add

ReadRegister#1

ReadRegister#2

WriteRegister

DataPort#1

Port#2

ALU

CLK

Interconnections

Critical path

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Datapath Components for MIPS lw/sw

lw R1, -100(R2)sw R1, -100(R2)

PC

address Inst.

R1

R2

-100

lw/sw

ReadRegister#1

ReadRegister#2

WriteRegister

DataPort#1

Port#2

ALU

REGISTERS

ROM

InstructionMemory

Data Memory

RAM

DataIn

Address

DataOut

16

SIGN-EXTEND16 32

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Connections for lwlw R1, -100(R2)

PC

address Inst.

R1

R2

-100

lw

ReadRegister#1

ReadRegister#2

WriteRegister

DataPort#1

Port#2

ALU

REGISTERS

ROM

InstructionMemory

Data Memory

RAM

DataIn

Address

DataOut

16

SIGN-EXTEND16 32

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Critical Path for lwlw R1, -100(R2)

PC

address Inst.

R1 (rt)

R2 (rs)

-100

lw

ReadRegister#1

ReadRegister#2

WriteRegister

DataPort#1

Port#2

ALU

REGISTERS

ROM

InstructionMemory

Data Memory

RAM

DataIn

Address

DataOut

16 (Imm)

SIGN-EXTEND16 32

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Connections for swsw R1, -100(R2)

PC

address Inst.

R1

R2

-100

sw

ReadRegister#1

ReadRegister#2

WriteRegister

DataPort#1

Port#2

ALU

REGISTERS

ROM

InstructionMemory

Data Memory

RAM

DataIn

Address

DataOut

16

SIGN-EXTEND16 32

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Critical Path for swsw R1, -100(R2)

PC

address Inst.

R1

R2

-100

sw

ReadRegister#1

ReadRegister#2

WriteRegister

DataPort#1

Port#2

ALU

REGISTERS

ROM

InstructionMemory

Data Memory

RAM

DataIn

Address

DataOut

16

SIGN-EXTEND16 32

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Datapath Connections for MIPS add and lw

add R1, R2, R3

PC address Inst.

R1R2R3add

ReadRegister#1

ReadRegister#2

WriteRegisterData

Port#1

Port#2ALU

CLK

lw R1, -100(R2)

PC address Inst.

R1R2-100lw

ReadRegister#1

ReadRegister#2

WriteRegisterData

Port#1

Port#2ALU

InstructionMemory

Data Memory

RAMDataIn

Address

DataOut

16

SIGN-EXTEND16 32

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Datapath Connections for MIPS add and lw

PC address Inst.

R1R2-100lw

ReadRegister#1

ReadRegister#2

WriteRegisterData

Port#1

Port#2ALU

InstructionMemory

Data Memory

RAMDataIn

Address

DataOut

16

SIGN-EXTEND16 32

NEED MUX

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Combined Datapath: R-Type and Load/Store Instructions

5 516

RD1

RD2

RN1 RN2 WN

WD

RegWrite

Register File

Operation

ALU

3

EXTND

16 32

Zero

RD

WD

MemRead

DataMemory

ADDRMemWrite

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Instruction32

MUX

MUXALUSrc

MemtoReg

PC address Inst.

R1R2-100lw

ReadRegister#1

ReadRegister#2

WriteRegisterData

Port#1

Port#2ALU

InstructionMemory

Data Memory

RAMDataIn

Address

DataOut

16

SIGN-EXTEND16 32

NEED MUX

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Combined Datapath: Executing an R-Type Instruction

add rd,rs,rt5 516

RD1

RD2

RN1 RN2 WN

WD

RegWrite

Register File

Operation

ALU

3

EXTND

16 32

Zero

RD

WD

MemRead

DataMemory

ADDRMemWrite

5

Instruction32

MUX

MUXALUSrc

MemtoReg

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Combined Datapath: Executing a load instruction

lw rt,offset(rs)5 516

RD1

RD2

RN1 RN2 WN

WD

RegWrite

Register File

Operation

ALU

3

EXTND

16 32

Zero

RD

WD

MemRead

DataMemory

ADDRMemWrite

5

Instruction32

MUX

MUXALUSrc

MemtoReg

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Combined Datapath: Executing a store instruction

sw rt,offset(rs)5 516

RD1

RD2

RN1 RN2 WN

WD

RegWrite

Register File

Operation

ALU

3

EXTND

16 32

Zero

RD

WD

MemRead

DataMemory

ADDRMemWrite

5

Instruction32

MUX

MUXALUSrc

MemtoReg

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Summary

• Read Ch B.7-9